mirror of https://github.com/efabless/caravel.git
update signoff scripts to add signoff results of SoC modules to `./<MCW_ROOT>/signoff/`
add false paths and case analysis reports for top-level caravel STA run
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@ -41,7 +41,7 @@ optional arguments:
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-a, --all run all checks
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````
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### How to run Caravel top-level STA including user project wrapper
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1. edit in [pt_sta.tcl](./pt_sta.tcl) the spef mapping section to add the user project module instantiated in user project wrapper
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1. edit in [pt_sta.tcl](https://github.com/efabless/caravel/blob/caravel_redesign/scripts/pt_sta.tcl#L69) the spef mapping section to add the user project module instantiated in user project wrapper
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2. run the command
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````
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python3 signoff_automation.py -d caravel -sta
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@ -6,7 +6,7 @@ import os
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def klayout_gds_drc_check(design_name, drc_script_path, gds_input_file_path, signoff_directory, logs_directory):
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report_file_path = signoff_directory / 'caravel' / f'{design_name}_klayout_drc.xml'
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report_file_path = signoff_directory / f'{design_name}' / f'{design_name}_klayout_drc.xml'
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run_drc_check_cmd = ['klayout', '-b', '-r', drc_script_path,
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'-rd', f"input={gds_input_file_path}",
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'-rd', f"report={report_file_path}",
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@ -233,29 +233,38 @@ if {\
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report_constraint -all_violators -significant_digits 4 -nosplit > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-all_viol.rpt
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report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-min_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-min_timing.rpt
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report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-max_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-max_timing.rpt
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if {$design == "caravel"} {
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report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group clk \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-clk-min_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-clk-min_timing.rpt
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report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group clk \
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-clk-max_timing.rpt
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report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hk_serial_clk \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-min_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-min_timing.rpt
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report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hk_serial_clk \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-max_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-max_timing.rpt
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report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hkspi_clk \
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hkspi_clk-max_timing.rpt
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report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hkspi_clk \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hkspi_clk-min_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hkspi_clk-min_timing.rpt
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report_timing -delay min -through [get_cells soc] -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-min_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-min_timing.rpt
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report_timing -delay max -through [get_cells soc] -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
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-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-max_timing.rpt
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-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-max_timing.rpt
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report_case_analysis -nosplit > $::env(OUT_DIR)/reports/${design}.case_analysis.rpt
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report_exceptions -nosplit > $::env(OUT_DIR)/reports/${design}.false_paths.rpt
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}
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write_sdf -version 3.0 -significant_digits 4 $::env(OUT_DIR)/sdf/${rc_corner}/${design}.${proc_corner}${proc_corner}.sdf
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@ -34,12 +34,12 @@ def build_caravel(caravel_root, mcw_root, pdk_root, log_dir, pdk_env):
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subprocess.run(build_cmd, stderr=build_log, stdout=build_log)
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def run_drc(caravel_root, log_dir, signoff_dir, pdk_root, design):
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def run_drc(design_root, log_dir, signoff_dir, pdk_root, design):
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klayout_drc_cmd = [
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"python3",
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"klayout_drc.py",
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"-g",
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f"{caravel_root}/gds/{design}.gds",
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f"{design_root}/gds/{design}.gds",
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"-l",
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f"{log_dir}",
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"-s",
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@ -383,6 +383,8 @@ if __name__ == "__main__":
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sta = args.primetime_sta
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design = args.design
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antenna = args.antenna
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if (design == "mgmt_core_wrapper" or design == "RAM128" or design == "RAM256"):
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signoff_dir = os.path.join(mcw_root, "signoff")
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if not os.path.exists(f"{log_dir}"):
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os.makedirs(f"{log_dir}")
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@ -423,7 +425,10 @@ if __name__ == "__main__":
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sta = True
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if drc:
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drc_p1 = run_drc(caravel_root, log_dir, signoff_dir, pdk_root, design)
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if (design == "mgmt_core_wrapper" or design == "RAM128" or design == "RAM256"):
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drc_p1 = run_drc(mcw_root, log_dir, signoff_dir, pdk_root, design)
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else:
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drc_p1 = run_drc(caravel_root, log_dir, signoff_dir, pdk_root, design)
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logging.info(f"Running klayout DRC on {design}")
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if lvs:
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lvs_p1 = run_lvs(
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