update signoff scripts to add signoff results of SoC modules to `./<MCW_ROOT>/signoff/`

add false paths and case analysis reports for top-level caravel STA run
This commit is contained in:
Passant 2022-10-15 13:34:45 -07:00
parent 94ab378af1
commit 9b80912487
4 changed files with 27 additions and 13 deletions

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@ -41,7 +41,7 @@ optional arguments:
-a, --all run all checks
````
### How to run Caravel top-level STA including user project wrapper
1. edit in [pt_sta.tcl](./pt_sta.tcl) the spef mapping section to add the user project module instantiated in user project wrapper
1. edit in [pt_sta.tcl](https://github.com/efabless/caravel/blob/caravel_redesign/scripts/pt_sta.tcl#L69) the spef mapping section to add the user project module instantiated in user project wrapper
2. run the command
````
python3 signoff_automation.py -d caravel -sta

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@ -6,7 +6,7 @@ import os
def klayout_gds_drc_check(design_name, drc_script_path, gds_input_file_path, signoff_directory, logs_directory):
report_file_path = signoff_directory / 'caravel' / f'{design_name}_klayout_drc.xml'
report_file_path = signoff_directory / f'{design_name}' / f'{design_name}_klayout_drc.xml'
run_drc_check_cmd = ['klayout', '-b', '-r', drc_script_path,
'-rd', f"input={gds_input_file_path}",
'-rd', f"report={report_file_path}",

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@ -233,29 +233,38 @@ if {\
report_constraint -all_violators -significant_digits 4 -nosplit > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-all_viol.rpt
report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-min_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-min_timing.rpt
report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-max_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-max_timing.rpt
if {$design == "caravel"} {
report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group clk \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-clk-min_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-clk-min_timing.rpt
report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group clk \
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-clk-max_timing.rpt
report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hk_serial_clk \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-min_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-min_timing.rpt
report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hk_serial_clk \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-max_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hk_serial_clk-max_timing.rpt
report_timing -delay max -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hkspi_clk \
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hkspi_clk-max_timing.rpt
report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit -group hkspi_clk \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hkspi_clk-min_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-hkspi_clk-min_timing.rpt
report_timing -delay min -through [get_cells soc] -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-min_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-min_timing.rpt
report_timing -delay max -through [get_cells soc] -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
-max_paths 1000 -nworst 10 -slack_lesser_than 100 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-max_timing.rpt
-max_paths 10000 -nworst 10 -slack_lesser_than 10 -significant_digits 4 -include_hierarchical_pins > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-soc-max_timing.rpt
report_case_analysis -nosplit > $::env(OUT_DIR)/reports/${design}.case_analysis.rpt
report_exceptions -nosplit > $::env(OUT_DIR)/reports/${design}.false_paths.rpt
}
write_sdf -version 3.0 -significant_digits 4 $::env(OUT_DIR)/sdf/${rc_corner}/${design}.${proc_corner}${proc_corner}.sdf

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@ -34,12 +34,12 @@ def build_caravel(caravel_root, mcw_root, pdk_root, log_dir, pdk_env):
subprocess.run(build_cmd, stderr=build_log, stdout=build_log)
def run_drc(caravel_root, log_dir, signoff_dir, pdk_root, design):
def run_drc(design_root, log_dir, signoff_dir, pdk_root, design):
klayout_drc_cmd = [
"python3",
"klayout_drc.py",
"-g",
f"{caravel_root}/gds/{design}.gds",
f"{design_root}/gds/{design}.gds",
"-l",
f"{log_dir}",
"-s",
@ -383,6 +383,8 @@ if __name__ == "__main__":
sta = args.primetime_sta
design = args.design
antenna = args.antenna
if (design == "mgmt_core_wrapper" or design == "RAM128" or design == "RAM256"):
signoff_dir = os.path.join(mcw_root, "signoff")
if not os.path.exists(f"{log_dir}"):
os.makedirs(f"{log_dir}")
@ -423,7 +425,10 @@ if __name__ == "__main__":
sta = True
if drc:
drc_p1 = run_drc(caravel_root, log_dir, signoff_dir, pdk_root, design)
if (design == "mgmt_core_wrapper" or design == "RAM128" or design == "RAM256"):
drc_p1 = run_drc(mcw_root, log_dir, signoff_dir, pdk_root, design)
else:
drc_p1 = run_drc(caravel_root, log_dir, signoff_dir, pdk_root, design)
logging.info(f"Running klayout DRC on {design}")
if lvs:
lvs_p1 = run_lvs(