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Kevin Liao 965fbdbfea correct to sky130_fd_sc_hd__sdfrtp_1 2021-01-26 15:36:33 -08:00
..
README.md [Doc] Add README to HDL common files 2020-11-28 17:37:36 -07:00
caravel_fpga_wrapper_hd.v [FPGA1212_v1.1] Added OpenFPGA task and verilog netlist 2020-12-02 01:43:05 -07:00
caravel_fpga_wrapper_hd_template.v [FPGA1212_v1.1] Added OpenFPGA task and verilog netlist 2020-12-02 01:43:05 -07:00
caravel_gl_include_netlists.v [HDL] Add include netlist for Caravel RTL netlists 2020-12-15 16:14:01 -07:00
caravel_qlsofa_hd_rtl_include_netlists.v [HDL] Update caravel include netlist to use simulation without power pins 2020-12-16 20:26:53 -07:00
caravel_wrapper_pin_assignment_v1.0.json [HDL] Bug fix in the pin assignment due to the conflicts on sc_tail and ccff_tail 2020-11-30 10:29:05 -07:00
caravel_wrapper_pin_assignment_v1.1.json [HDL] Patch pin assignment names to be consistent with post-PnR netlists 2020-12-02 14:02:18 -07:00
custom_cell_mux_primitive_generator.py [HDL] Update code generator for the changes on custom cell names 2020-12-18 20:25:50 -07:00
digital_io_hd.v [HDL] Add digital I/O self testing testbench 2020-12-11 16:11:12 -07:00
digital_io_hd_primitives.v [HDL] Add primitive include lines for digital I/O built with HD cells 2020-12-06 11:35:35 -07:00
fd_hd_mux_custom_cells_tt.v [HDL] Bug fix due to custom cell name changing 2020-12-18 20:24:55 -07:00
ql_ccff.v correct to sky130_fd_sc_hd__sdfrtp_1 2021-01-26 15:36:33 -08:00
ql_io_logic.v created for quicklogic special io logic 2021-01-12 21:14:09 -08:00
ql_iso_io_logic.v rename module name to IO from EMBEDDED_IO_HD 2021-01-21 20:52:16 -08:00
sky130_fd_sc_hd_wrapper.v [FPGA1212_v1.1] Added OpenFPGA task and verilog netlist 2020-12-02 01:43:05 -07:00
skywater_function_verification.v [HDL] Add preprocessing flags for running functional verification 2020-11-05 11:29:23 -07:00
user_project_wrapper.v [HDL] Bug fix in VSS port naming 2020-12-16 13:40:09 -07:00
user_project_wrapper_integration.v [CI] Precheck related updates 2020-12-17 15:01:49 -07:00
wrapper_lines_generator.py [HDL] bug fix in wrapper line generator 2020-11-29 12:47:22 -07:00

README.md

Skywater PDK

This directory contains the HDL netlists and code generator for FPGA fabrics.

  • caravel_fpga_wrapper_hd.v: The wrapper for FPGA fabric to interface the Caravel SoC, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library. This file is automatically generated by a Python script
  • caravel_defines.v: The parameters required for Caravel wrapper HDL codes
  • caravel_fpga_wrapper_hd_template.v: The template HDL codes for the wrapper
  • digital_io_hd.v: the I/O cell used by High-density FPGA, which is technology mapped to the Skywater 130nm Foundry High-Density Standard Cell Library.
  • sky130_fd_sc_hd_wrapper.v: Wrapper codes for the standard cells from the Skywater 130nm Foundry High-Density Standard Cell Library
  • skywater_function_verification.v: Include pre-processing flags to enable functional verification for FPGAs
  • wrapper_lines_generator.py: Python script to generate the wrapper caravel_fpga_wrapper_hd.v