mirror of https://github.com/lnis-uofu/SOFA.git
21 lines
494 B
Verilog
21 lines
494 B
Verilog
`timescale 1ns/1ps
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//-----------------------------------------------------
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// Function: a wrapper for the MUX2 required by carry logic
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//-----------------------------------------------------
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module sky130_fd_sc_hd__mux2_1_wrapper (
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input A0,
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input A1,
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input S,
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output X
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);
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sky130_fd_sc_hd__mux2_1 MUX2 (.A0(A0),
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.A1(A1),
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.S(S),
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.X(X)
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);
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endmodule
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