mirror of https://github.com/lnis-uofu/SOFA.git
107 lines
2.7 KiB
Verilog
107 lines
2.7 KiB
Verilog
`default_nettype wire
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/*
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*-------------------------------------------------------------
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*
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* user_project_wrapper for post-PnR FPGA netlists
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*
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* This wrapper will instanciate the top-level module of FPGA IP
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* and wire the pins to the wrapper interface that Caravel requires
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*-------------------------------------------------------------
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*/
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module user_project_wrapper #(
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parameter BITS = 32
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)(
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`ifdef USE_POWER_PINS
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oen,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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// Analog (direct connection to GPIO pad---use with caution)
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// Note that analog I/O is not available on the 7 lowest-numbered
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// GPIO pads, and so the analog_io indexing is offset from the
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// GPIO indexing by 7.
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inout [`MPRJ_IO_PADS-8:0] analog_io,
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// Independent clock (on independent integer divider)
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input user_clock2
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);
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/*--------------------------------------*/
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/* User project is instantiated here */
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/*--------------------------------------*/
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fpga_top mprj (
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`ifdef USE_POWER_PINS
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.vdda1(vdda1), // User area 1 3.3V power
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.vdda2(vdda2), // User area 2 3.3V power
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.vssa1(vssa1), // User area 1 analog ground
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.vssa2(vssa2), // User area 2 analog ground
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.vccd1(vccd1), // User area 1 1.8V power
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.vccd2(vccd2), // User area 2 1.8V power
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.vssd1(vssd1), // User area 1 digital ground
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.vssd2(vssd2), // User area 2 digital ground
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.VDD(vccd1),
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.VSS(vssd1),
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`endif
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// MGMT core clock and reset
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.wb_clk_i(wb_clk_i),
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.wb_rst_i(wb_rst_i),
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// MGMT SoC Wishbone Slave
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.wbs_cyc_i(wbs_cyc_i),
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.wbs_stb_i(wbs_stb_i),
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.wbs_we_i(wbs_we_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_dat_i(wbs_dat_i),
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.wbs_ack_o(wbs_ack_o),
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.wbs_dat_o(wbs_dat_o),
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// Logic Analyzer
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.la_data_in(la_data_in),
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.la_data_out(la_data_out),
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.la_oen (la_oen),
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// IO Pads
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.io_in (io_in),
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.io_out(io_out),
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.io_oeb(io_oeb)
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);
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endmodule // user_project_wrapper
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`default_nettype wire
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