tangxifan
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87f79d78bb
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[CI] Add wrapper generator examples to CI
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2020-12-06 01:39:16 -07:00 |
tangxifan
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696529b43d
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[Script] Increase routing chan width from 40 to 60 for version 1.2
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2020-12-06 01:39:16 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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f572be8fc2
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Merge pull request #56 from lnis-uofu/xt_dev
Python script to adapt OpenFPGA netlist to use custom MUX cells
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2020-12-05 22:11:36 -07:00 |
tangxifan
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443eb12710
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[CI] Add test to CI
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2020-12-05 21:17:59 -07:00 |
tangxifan
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22f2b3aa90
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[HDL] Add python script to adapt OpenFPGA MUX primitives to use custom cells
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2020-12-05 21:14:56 -07:00 |
tangxifan
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6039ae92ca
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[Arch] Bug fix for buffering two-level routing multiplexers using custom cells
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2020-12-05 19:37:34 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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52413059f6
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Merge pull request #55 from lnis-uofu/xt_dev
Major Changes in Documentation
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2020-12-04 14:47:52 -07:00 |
tangxifan
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3a75e079ba
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[Doc] Update the frontpage README
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2020-12-04 14:09:40 -07:00 |
tangxifan
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f766052bf7
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[Doc] Add route W to device comparison
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2020-12-04 13:41:47 -07:00 |
tangxifan
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156e1d007c
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[Doc] Add missing figure and bug fix
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2020-12-04 13:34:41 -07:00 |
tangxifan
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1948f000e0
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[Doc] Reorganize documentation for SOFA HD device family
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2020-12-04 12:02:30 -07:00 |
tangxifan
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6fca7b9641
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[Doc] Add figures about fle architecture v1.1
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2020-12-04 09:27:11 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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a09933cb75
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Merge pull request #54 from lnis-uofu/xt_dev
Critical Patches on Simulation Scripts and Testbenches
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2020-12-03 17:20:02 -07:00 |
tangxifan
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51167f871e
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[Testbench] Patch ccff test
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2020-12-02 20:07:36 -07:00 |
tangxifan
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ce058447f2
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[MSIM] Bug fix in reporting errors
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2020-12-02 20:07:16 -07:00 |
tangxifan
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2db2b468fe
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[Script] Try auto number of simulation clock cycles
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2020-12-02 19:33:28 -07:00 |
tangxifan
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3a097b38af
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[CI] Remove the out-of-data tests
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2020-12-02 18:00:48 -07:00 |
tangxifan
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930f7ec486
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[Script] Remove task run for redundant architectures
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2020-12-02 17:56:58 -07:00 |
tangxifan
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7b637e6676
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[Testbench] Bug fix in post PnR testbench templates
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2020-12-02 17:50:49 -07:00 |
tangxifan
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b966829566
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[Script] Force a fixed number of clock cycles in simulation to avoid false-positive
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2020-12-02 17:50:23 -07:00 |
tangxifan
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a19c9bdbda
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[CI] Add CCFF and SCFF testbench conversion to CI test
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2020-12-02 15:30:54 -07:00 |
tangxifan
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6814b3bb60
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[Testbench] Now ccff and scff testbench template have multiple versions corresponding to the FPGA variants
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2020-12-02 15:22:19 -07:00 |
tangxifan
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4875b2de95
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[HDL] Patch pin assignment names to be consistent with post-PnR netlists
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2020-12-02 14:02:18 -07:00 |
tangxifan
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06731e092e
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[Arch] Patch reset port name to be consistent with post-PnR netlist
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2020-12-02 13:46:40 -07:00 |
tangxifan
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20cba3f558
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[Testbench] Add testbench for post-PnR verification for FPGA with reset
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2020-12-02 13:43:06 -07:00 |
tangxifan
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ea3165b14d
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Merge branch 'master' into xt_dev
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2020-12-02 13:27:50 -07:00 |
tangxifan
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b9053269e9
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Merge pull request #52 from lnis-uofu/ganesh_dev
Ganesh dev
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2020-12-02 13:10:35 -07:00 |
Ganesh Gore
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0cc5b492d2
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[Cleanup] Removed/Ignored testbench files from generated source
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2020-12-02 12:03:24 -07:00 |
tangxifan
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61163de580
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[Testbench] Correct path to post-pnR netlists and prepare for sign-off on FPGA with reset
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2020-12-02 12:00:28 -07:00 |
Ganesh Gore
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361cd2d9e1
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-12-02 10:56:59 -07:00 |
Ganesh Gore
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923a502c24
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[FPGA1212_v1.1] Added PostPnR files
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2020-12-02 01:43:58 -07:00 |
Ganesh Gore
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f385c0ca11
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[FPGA1212_v1.1] Added OpenFPGA task and verilog netlist
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2020-12-02 01:43:05 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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07d1962051
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Merge pull request #51 from lnis-uofu/xt_dev
Add new architecture files which use custom cells based on Skywater HD library
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2020-12-01 22:16:49 -07:00 |
tangxifan
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b5abfdd994
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[Arch] enable local encoders
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2020-12-01 20:56:53 -07:00 |
tangxifan
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fc92dceb94
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[CI] Add new arch to CI test
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2020-12-01 20:55:10 -07:00 |
tangxifan
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3b6f3b0691
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[Arch] Bug fix in new arch
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2020-12-01 20:49:02 -07:00 |
tangxifan
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147dd8d606
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[Script] Add task run for custom cell FPGA architectures
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2020-12-01 20:22:16 -07:00 |
tangxifan
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454ea09dc4
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[Arch] Add architecture using custom cells
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2020-12-01 20:19:22 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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29a9dea3ca
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Merge pull request #50 from lnis-uofu/xt_dev
Add wrapper generator examples to CI
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2020-12-01 15:45:35 -07:00 |
tangxifan
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f2056a9bf9
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[Git] Ignore .v as LFS files
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2020-12-01 14:50:20 -07:00 |
tangxifan
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4594be46c8
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[CI] Patch github repo path to sync with OpenFPGA repo movement
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2020-12-01 11:58:19 -07:00 |
tangxifan
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83bd343f70
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[CI] Add wrapper generator examples to CI
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2020-12-01 11:32:27 -07:00 |
Ganesh Gore
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fd7a65c756
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Merge remote-tracking branch 'origin/master' into ganesh_dev
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2020-12-01 11:29:15 -07:00 |
Ganesh Gore
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a134cffb9d
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Added verilog files only in testbench directory in gitLFS
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2020-12-01 11:23:02 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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95cbc60cc2
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Merge pull request #49 from LNIS-Projects/xt_dev
Increase routing chan width from 40 to 60 for the architecture using reset and soft adders
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2020-12-01 11:21:31 -07:00 |
tangxifan
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0eb1b68bee
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[Script] Increase routing chan width from 40 to 60 for version 1.2
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2020-12-01 10:17:47 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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8713eb3c5b
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Merge pull request #48 from LNIS-Projects/xt_dev
Add Continuous Integration
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2020-12-01 08:56:35 -07:00 |
tangxifan
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d867dbb1bf
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[Testbench] Bug fix in calling sub python script
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2020-12-01 08:14:43 -07:00 |
tangxifan
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11d4b156b4
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[Testbench] Bug fix in finding scripts
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2020-11-30 22:41:29 -07:00 |
tangxifan
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6d5bb2d794
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[CI] Bug fix
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2020-11-30 22:38:24 -07:00 |