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502 Commits 16 Branches 1 Tag 1.8 GiB
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502 Commits

Author SHA1 Message Date
tangxifan 899018d503 [HDL] Bug fix in wrapper template 2020-11-29 12:38:25 -07:00
tangxifan ea758cd5b1 [HDL] Update wrapper template as most codes can be auto-generated 2020-11-29 12:36:23 -07:00
tangxifan f78a53fd03 [HDL] Add tab to wrapper line generation 2020-11-29 12:35:24 -07:00
tangxifan ebd3053a4e [HDL] bug fix in wrapper generator 2020-11-29 12:31:32 -07:00
tangxifan 0e964534bc [HDL] bug fix in wrapper line generator 2020-11-29 12:01:15 -07:00
tangxifan 9622b44554 [HDL] Bug fix in JSON file syntax 2020-11-29 11:59:56 -07:00
tangxifan 27da78fe29 [HDL] Update wrapper line generator to parse json data 2020-11-29 11:57:34 -07:00
tangxifan 329b6644f3 [Script] Bug fix in creating directories for verification task 2020-11-29 11:02:23 -07:00
Ganesh Gore 20dc203b31 [FPGA1212_v1] Module level results 2020-11-29 11:02:17 -07:00
Ganesh Gore 225feaef3c [FPGA1212_v1] Added top-level pnr screenshots 2020-11-29 10:59:15 -07:00
tangxifan 4ec490645d Merge branch 'master' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev 2020-11-29 10:35:40 -07:00
tangxifan bc3d839e5b [HDL] Upgrading code generator for wrapper 2020-11-29 10:35:10 -07:00
tangxifan a50dfc09b5
Merge pull request #43 from LNIS-Projects/ganesh_dev 
[FPGA1212_V1] Updated design
 2020-11-29 10:34:29 -07:00
Ganesh Gore 7db7c240e3 [FPGA1212_V1] Updated design + Added buffer on IO_EN net + Tie Off floating module inputs + Complete DRC/Timing closed 2020-11-29 10:24:03 -07:00
tangxifan aac8ddc3ec [HDL] update json to ease parsing 2020-11-28 21:10:46 -07:00
tangxifan 47389a483e [HDL] Add json description for pin assignment v1.0 2020-11-28 20:55:41 -07:00
tangxifan 54eb5b469b [Doc] Fix pin direction typo in I/O resource map 2020-11-28 20:13:05 -07:00
tangxifan aff43bf473 [Doc] Add README to HDL common files 2020-11-28 17:37:36 -07:00
Laboratory for Nano Integrated Systems (LNIS) 90f4e3fa70
Merge pull request #42 from LNIS-Projects/xt_dev 
Push-button Modelsim Verification for Specific FPGA fabric
 2020-11-28 16:44:21 -07:00
tangxifan 969ef7976f [Testbench] Remove those with problems in convergence 2020-11-28 15:24:54 -07:00
tangxifan 3c685311e9 [Testbench] Bug fix for the ccff testbench to sync with latest netlist 2020-11-28 15:22:50 -07:00
tangxifan 4e9b07125e [Script] Bug fix 2020-11-28 15:01:09 -07:00
tangxifan d70bcbb7ca [Doc] Add README for Modelsim workspace 2020-11-28 14:59:26 -07:00
tangxifan d3b1562fa2 [Testbench] Rename top-level module to be compatible to Modelsim task run scripts 2020-11-28 14:55:17 -07:00
tangxifan ee92b15f0e [Script] Bug fix in modelsim task-run script 2020-11-28 14:50:39 -07:00
tangxifan 2380783808 [Testbench] Remove post pnr testbenches that can be auto-generated 2020-11-28 14:46:27 -07:00
tangxifan 8374fcfd4e [Script] Rectify output messages 2020-11-28 14:41:48 -07:00
tangxifan 396988b1b6 [Script] Now testbench generator requires a specific dir name 2020-11-28 14:39:18 -07:00
tangxifan e88a33831c [Testbench] Update scripts to rename top-level module for post-PnR testbenches 2020-11-28 14:29:56 -07:00
tangxifan 1b7b247097 [Testbench] Rename to be compatible with Modelsim run scripts 2020-11-28 14:25:55 -07:00
tangxifan 8c44532e4e [Script] Add python script to run all the testbenches in a given repo 2020-11-28 14:24:27 -07:00
tangxifan 56cbe48ad6 [Script] Disable debugging log in single Modelsim verification task 2020-11-28 13:53:14 -07:00
tangxifan 9c7ec9bd61 [Script] Now python script for post-pnr Modelsim simulation works 2020-11-28 13:00:21 -07:00
tangxifan a9b94d4303 [Testbench] Update top-level module name for post PnR testbenches 2020-11-28 12:59:59 -07:00
tangxifan b2ebac3b23 [Testbench] Rename post-PnR testbenches to ease modelsim batch jobs 2020-11-28 11:14:34 -07:00
tangxifan 0c9953a26e [Testbench] Update post-PnR testbenches to synchornize with latest netlist 2020-11-28 11:09:55 -07:00
tangxifan 0f0133951c [Script] Update modelsim script for post-PnR verification 2020-11-28 11:07:39 -07:00
tangxifan f435d80dcc
Merge pull request #41 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-11-27 22:55:45 -07:00
Ganesh Gore 66d09da857 [FPGA1212_v1] Updated the PostPnR Netlist and PnR Files 2020-11-27 22:11:51 -07:00
Ganesh Gore ce4a6f72f5 [FPGA1212_v1] Updated the task and PrePNR Verilog netlist 2020-11-27 22:08:16 -07:00
Ganesh Gore da097413b0 [Cleanup] Removed buggy hierarchical flow files 2020-11-27 22:00:43 -07:00
Laboratory for Nano Integrated Systems (LNIS) 4c8e94722c
Merge pull request #40 from LNIS-Projects/xt_dev 
New Architecture: Support both Reset pins in FFs and Soft Adders
 2020-11-27 20:00:05 -07:00
tangxifan c7ea3f3936 [Arch] Bug fix in the arch with reset and soft adder 2020-11-27 19:54:31 -07:00
tangxifan 6a12cdbad1 [Script] Add task run for the architecture with both reset and soft adders 2020-11-27 18:15:05 -07:00
tangxifan 14c21378b8 [Arch] Add new architecture using reset and softadder 2020-11-27 18:12:06 -07:00
Ganesh Gore 5be185e7a5 Merge remote-tracking branch 'origin/master' into ganesh_dev 2020-11-27 17:51:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 9102b7ec5e
Merge pull request #39 from LNIS-Projects/xt_dev 
New Architecture: Support Carry Adders which are Implemented by LUTs
 2020-11-27 16:41:57 -07:00
tangxifan efab96d2dd [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
tangxifan e5a66dd47f [Script] Add task run for softadder architecture 2020-11-27 16:14:14 -07:00
tangxifan 31dcd4a17f [HDL] Add a wrapper for HD MUX2 cell required by carry logic 2020-11-27 16:01:27 -07:00