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737 Commits

Author SHA1 Message Date
tangxifan 6939ac9676 [Doc] Update required packages for documentation compilation; So that svg image can display in PDF 2021-04-02 09:57:27 -06:00
tangxifan 1f506fb8d8
Merge pull request #103 from lnis-uofu/xt_dev 
Add report timing scripts
 2021-04-02 09:33:06 -06:00
tangxifan 8d6f66dfae
Merge branch 'master' into xt_dev 2021-04-01 22:17:22 -06:00
tangxifan 8196514c26 [Arch] Bug fix 2021-04-01 22:16:44 -06:00
GrantBrown1994 166ea43d96 Custom cell documentation added 2021-04-01 21:42:42 -06:00
tangxifan b22584e7a1 [MISC] Bug fixes for wrong paths in task configuration files; typo in arch files 2021-04-01 21:16:08 -06:00
tangxifan 4aea849cf9 [Script] Add design varaibles to task configuration files 2021-04-01 21:06:22 -06:00
tangxifan 7059c6a014 [Arch] Add timing variables for CHD arch but will update later 2021-04-01 21:05:53 -06:00
tangxifan 36b871bcbb [Arch] Name change for FF CLK2Q vairable 2021-04-01 21:00:53 -06:00
tangxifan cf6bdf0768 [Arch] Update QLSOFA arch with timing variables 2021-04-01 21:00:09 -06:00
tangxifan c9b4699508 [Arch] Add QLSOFA timing at TT corner 2021-04-01 20:59:47 -06:00
tangxifan 881d07a123 [Arch] Bug fix 2021-04-01 20:43:24 -06:00
tangxifan 2afd42bb45 [Arch] Explicit comment SOFA HD arch 2021-04-01 20:31:13 -06:00
tangxifan 7e4595068a [Script] Add design variables to task configuration files 2021-04-01 20:29:30 -06:00
tangxifan 54df2a4f97 [Arch] Update SOFA HD arch to use timing variables 2021-04-01 20:29:13 -06:00
tangxifan f28ff97b8b [Arch] Move timing values to design variable yml so that we can reuse arch XML to model timing in different corners 2021-04-01 20:28:38 -06:00
tangxifan 514dbf045d [Script] Update report timinig script for CLB 2021-04-01 18:10:06 -06:00
tangxifan 12af3b5fa3 [Script] Update report timing script for I/O 2021-04-01 18:09:31 -06:00
tangxifan fdb37e0559 [Script] formatting 2021-04-01 18:09:17 -06:00
tangxifan db203b3690 [Script] Update report timing script for switch blocks in the purpose of one-shot report generation 2021-04-01 18:04:56 -06:00
tangxifan 7b49fa0684 [Script] Update report timing script for connection blocks so that timing reports are generated in 1 shot 2021-04-01 17:53:53 -06:00
tangxifan 062120ffd9 [Arch] Update timing for SOFA architecture 2021-04-01 16:39:19 -06:00
tangxifan 1b59daebc6 [Script] Add comments 2021-04-01 15:59:33 -06:00
tangxifan 0ba5ec9b93 [Script] Add report timing script for I/O 2021-04-01 15:58:54 -06:00
tangxifan 3ed41a4704 [Script] Add report timing script for CLB 2021-04-01 15:43:51 -06:00
tangxifan a640f589ea [Script] Add report timing script for switch blocks 2021-04-01 14:45:00 -06:00
tangxifan 17033730fe [Script] Update report timing script for CBs 2021-04-01 14:38:07 -06:00
tangxifan 128e8e6aa3 [Script] Add report timing script for connection blocks 2021-03-31 19:40:36 -06:00
tangxifan ad93d26250
Merge pull request #101 from lnis-uofu/xt_dev 
Fix the mismatched name of Quicklogic's yosys scripts in task configuration files
 2021-03-31 15:15:51 -06:00
tangxifan bafecc625b [Script] Bug fix 2021-03-31 14:20:37 -06:00
tangxifan 7faf529538 [Script] Bypass jpng benchmark 2021-03-31 13:17:28 -06:00
tangxifan 775881e529 [Script] Bypass cavlc due to yosys synthesis problems 2021-03-31 12:29:24 -06:00
tangxifan 7d8812b844 [Script] Add missing QL synthesis arguments 2021-03-31 11:52:21 -06:00
tangxifan 7643950572 [Script] Fix the mismatched name of Quicklogic's yosys scripts in task configuration files 2021-03-31 10:54:10 -06:00
tangxifan db791e1820
Merge pull request #98 from mithro/patch-1 
Fix spelling of floorplan.
 2021-02-13 15:48:09 -07:00
Tim Ansell 286ebc7da2
Fix spelling of floorplan. 2021-02-13 14:05:46 -08:00
Ganesh Gore a203d2aeee [DRCFix] Fixed filler cell boundary SOFA CHD 2021-02-10 23:29:18 -07:00
Ganesh Gore 7309d3822c [DRCFix] Fixed filler cell boundary 2021-02-10 22:43:08 -07:00
Ganesh Gore f8c34abb2f [DRCFix] Fixed filler cell boundary 2021-02-10 15:29:34 -07:00
Ganesh Gore 9091298772 [DRCfix] Used fill and decap cells as fillers 2021-02-09 16:27:46 -07:00
ganeshgore 5519215882
Merge pull request #95 from lnis-uofu/FPGA1212_QLSOFA_arch_typo 
Fix parsing error in FPGA1212_QLSOFA arch file.
 2021-02-09 08:29:46 -07:00
Ganesh Gore a1af3743ef [DRCfix] Swapped fill cell with decap 2021-02-08 22:58:28 -07:00
Ganesh Gore 3d9748aa17 [DRCfix] QLSOFA swapped fill cell with decap 2021-02-08 22:34:09 -07:00
Ganesh Gore bf96303eec [GDS] Replaced fill cells by decap cells 2021-02-08 17:26:58 -07:00
tpagarani aff48898e2
Merge pull request #94 from antmicro/comment-shift-reg 
Commented out shift_register mode in k4_N8 VPR architecture.
 2021-02-08 13:39:41 -05:00
tpagarani cbaf92f990
Merge pull request #96 from antmicro/k4_N8-io-reg-map-fix 
Fixed IO register pb_type map
 2021-02-08 13:38:59 -05:00
Maciej Kurc 0823e7e878 Corrected destination pb_type offsets for IO registers in k4_N8 OpenFPGA arch XML. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-08 10:41:48 +01:00
WRansohoff b4e3440972
Fix parsing error in FPGA1212_QLSOFA arch file. 
I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with:

`python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`
 2021-02-05 11:36:29 -06:00
Maciej Kurc 63f210bc3d Commented out shift_register mode in k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-04 15:08:58 +01:00
tpagarani da52aa67eb
Merge pull request #91 from lnis-uofu/ql_ccff_dummy_stdcell_pointer 
(1)CFG_DONE to add is_config_enable(2)reset default=1 under tile_anno…
 2021-02-04 01:06:01 -05:00