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[Arch] Name change for FF CLK2Q vairable

This commit is contained in:
tangxifan 2021-04-01 21:00:53 -06:00
parent cf6bdf0768
commit 36b871bcbb
2 changed files with 5 additions and 5 deletions
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2
ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
View File

@ -11,7 +11,7 @@ L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_CLK2Q_DELAY: 0.43e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9

8
ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
View File

@ -365,7 +365,7 @@
<clock name="clk" num_pins="1"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
<T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@ -432,7 +432,7 @@
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@ -489,7 +489,7 @@
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
@ -526,7 +526,7 @@
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">