From 36b871bcbbb87b9fb1033bd33691316ec8be02d9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 1 Apr 2021 21:00:53 -0600
Subject: [PATCH] [Arch] Name change for FF CLK2Q vairable

---
 ...nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml | 2 +-
 ...register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
index 98481e8..82c1658 100644
--- a/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
+++ b/ARCH/timing_annotation/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm_timing_tt_025C_1v80.yml
@@ -11,7 +11,7 @@ L4_WIRE_C: 1e-12
 INPAD_DELAY: 0.11e-9
 OUTPAD_DELAY: 0.11e-9
 FF_T_SETUP: 0.39e-9
-FF_CLK2Q_DELAY: 0.43e-9
+FF_T_CLK2Q: 0.43e-9
 LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
 LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
 LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 838f202..1730839 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -365,7 +365,7 @@
               <clock name="clk" num_pins="1"/>
               <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
               <T_setup value="${FF_T_SETUP}" port="ff.DI" clock="clk"/>
-              <T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>         
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@@ -432,7 +432,7 @@
                 <output name="Q" num_pins="1" port_class="Q"/>
                 <clock name="clk" num_pins="1" port_class="clock"/>
                 <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
+                <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
               </pb_type>
               <interconnect>
                 <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
@@ -489,7 +489,7 @@
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
               <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
@@ -526,7 +526,7 @@
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
               <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="${FF_CLK2Q_DELAY}" port="ff.Q" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="shift_reg.reg_in" output="ff[0].D">