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[Arch] Bug fix

This commit is contained in:
tangxifan 2021-04-01 22:16:44 -06:00
parent b22584e7a1
commit 8196514c26
1 changed files with 1 additions and 1 deletions
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ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -530,7 +530,7 @@
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
<T_clock_to_Q max="{FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
<T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
</pb_type>
<interconnect>
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>