From 8196514c2699d61931bfcc9d84a56cfc986e6fac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 1 Apr 2021 22:16:44 -0600
Subject: [PATCH] [Arch] Bug fix

---
 ...adder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index d107281..fa538ba 100644
--- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -530,7 +530,7 @@
               <output name="Q" num_pins="1" port_class="Q"/>
               <clock name="clk" num_pins="1" port_class="clock"/>
               <T_setup value="${FF_T_SETUP}" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="{FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
+              <T_clock_to_Q max="${FF_T_CLK2Q}" port="ff.Q" clock="clk"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>