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Merge pull request #95 from lnis-uofu/FPGA1212_QLSOFA_arch_typo 

Fix parsing error in FPGA1212_QLSOFA arch file.
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ganeshgore 2021-02-09 08:29:46 -07:00 committed by GitHub
parent a1af3743ef b4e3440972
commit 5519215882
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1 changed files with 2 additions and 2 deletions
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FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml
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@ -230,10 +230,10 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name=="clb" port="clk" x="-1" y="-1"/>
<tile name="clb" port="clk" x="-1" y="-1"/>
</global_port>
<global_port name="Reset" is_reset="true" default_val="1">
<tile name=="clb" port="reset" x="-1" y="-1"/>
<tile name="clb" port="reset" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>