From b4e34409724fedd0338d8d74e25074cfe0ade454 Mon Sep 17 00:00:00 2001
From: WRansohoff <WRansohoff@users.noreply.github.com>
Date: Fri, 5 Feb 2021 11:36:29 -0600
Subject: [PATCH] Fix parsing error in FPGA1212_QLSOFA arch file.

I was pointed to this task as a starting point for generating an FPGA on the skywater PDK, and I think this small change is necessary to get the task to run with:

`python3 openfpga_flow/scripts/run_fpga_task.py FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/`
---
 .../FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml            | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml
index fbea0f4..aa409a0 100644
--- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml
+++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/openfpga_arch.xml
@@ -230,10 +230,10 @@
   </direct_connection>
   <tile_annotations>
       <global_port name="clk" is_clock="true" default_val="0">
-          <tile name=="clb" port="clk" x="-1" y="-1"/>
+          <tile name="clb" port="clk" x="-1" y="-1"/>
       </global_port>
       <global_port name="Reset" is_reset="true" default_val="1">
-          <tile name=="clb" port="reset" x="-1" y="-1"/>
+          <tile name="clb" port="reset" x="-1" y="-1"/>
       </global_port>
   </tile_annotations>
   <pb_type_annotations>