riscv
/
SOFA
mirror of https://github.com/lnis-uofu/SOFA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
711 Commits 16 Branches 1 Tag 1.8 GiB
Commit Graph

57 Commits

Author SHA1 Message Date
tangxifan 8196514c26 [Arch] Bug fix 2021-04-01 22:16:44 -06:00
tangxifan b22584e7a1 [MISC] Bug fixes for wrong paths in task configuration files; typo in arch files 2021-04-01 21:16:08 -06:00
tangxifan 36b871bcbb [Arch] Name change for FF CLK2Q vairable 2021-04-01 21:00:53 -06:00
tangxifan cf6bdf0768 [Arch] Update QLSOFA arch with timing variables 2021-04-01 21:00:09 -06:00
tangxifan 881d07a123 [Arch] Bug fix 2021-04-01 20:43:24 -06:00
tangxifan 2afd42bb45 [Arch] Explicit comment SOFA HD arch 2021-04-01 20:31:13 -06:00
tangxifan 54df2a4f97 [Arch] Update SOFA HD arch to use timing variables 2021-04-01 20:29:13 -06:00
tangxifan 062120ffd9 [Arch] Update timing for SOFA architecture 2021-04-01 16:39:19 -06:00
Maciej Kurc 63f210bc3d Commented out shift_register mode in k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-04 15:08:58 +01:00
Maciej Kurc a6db672595 Fixed incorrect IREG pack-pattern 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
Maciej Kurc 1e3490dc8d Added port relations to models and timing annotation to pb_types of the k4_N8 VPR architecture. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-02-03 11:10:39 +01:00
Tarachand Pagarani 3085cf7c2c remove io clk from output mux till prepack in VPR is updated to ignore physical mode 2021-01-20 01:16:59 -08:00
Tarachand Pagarani 72d8d20356 1. Add 4 clocks to IO interfaces 
2. Mux the clock with the output for sending the clock out of the FPGA
 2021-01-17 23:54:39 -08:00
Tarachand Pagarani ac355c370d merge latest changes from master 2021-01-15 00:26:25 -08:00
Tarachand Pagarani 3f5409eee2 add 4 global clocks 2021-01-14 02:28:07 -08:00
Lalit Sharma ba34ebb4e5 Removing commented sections/attributes. Also corrected indentation 2021-01-13 00:48:03 -08:00
Lalit Sharma 8f1bdc2e87 Updating interface definition for QL k4_N8 device 2021-01-11 23:20:49 +05:30
Tarachand Pagarani f04e72b5b3 create a copy of cout to connect to regular routing 2020-12-30 06:02:51 -08:00
Tarachand Pagarani 473e1d68a6 fix the carry in dangling 2020-12-29 19:04:56 -08:00
Tarachand Pagarani 61facff870 fix the carry in dangling and carry out accessible to regular routing 2020-12-29 18:54:48 -08:00
Tarachand Pagarani cbe50535ca further changes in architecture to make io interfaces routable 2020-12-28 08:35:17 -08:00
Tarachand Pagarani 474ed9b2ff Merge remote-tracking branch 'origin/master' into ql_ap3_arch_eval 2020-12-26 23:57:23 -08:00
Tarachand Pagarani 353207693a 1. added 32x32 fabric key\n 2. disable shift register packing due to routability failure\n 3. Disable IIR design due to routabiity failure in shift register mode\n 4. revert changes to QLSOFA architecture 2020-12-26 23:29:13 -08:00
Tarachand Pagarani 1aa0ef68e4 incoporated changes based on feedback from xifan 2020-12-24 23:05:47 -08:00
tangxifan 6a6b89e7b8 [Arch] Critical patch on dangling nets in logic elements 2020-12-21 22:23:41 -07:00
Tarachand Pagarani 01fabc65cc added a new architecture with LUT4, Soft adder and cross local routing with 24 clb inputs and feedback 2020-12-21 07:13:38 -08:00
Lalit Sharma c84c04c4b8 Increasing IO capacity to 32 2020-12-17 03:04:50 -08:00
Tarachand Pagarani 8502502b43 add 32x32 layout 2020-12-17 01:28:35 -08:00
Tarachand Pagarani 9f7fb8a34d modify carry chain to change output mux 2020-11-30 07:08:09 -08:00
tangxifan c7ea3f3936 [Arch] Bug fix in the arch with reset and soft adder 2020-11-27 19:54:31 -07:00
tangxifan 14c21378b8 [Arch] Add new architecture using reset and softadder 2020-11-27 18:12:06 -07:00
tangxifan efab96d2dd [Arch] Bug fix in softadder architecture 2020-11-27 16:36:31 -07:00
tangxifan 295df663bb [Arch] Add arch variant with soft adders 2020-11-27 15:57:05 -07:00
tangxifan f27424c803 [Arch] Bug fix in the architecture using reset 2020-11-27 15:04:19 -07:00
tangxifan c424c3d9a6 [Arch] Add a new variant with reset signals to FFs 2020-11-27 14:41:53 -07:00
tangxifan 864ed26c9a [Arch] Merge latest arch from QuickLogic team on AP3 device using VPR routing architecture 2020-11-27 10:11:40 -07:00
tangxifan 0fa3604b6c [Arch] Update arch to enable more routability in shift register mode 2020-11-25 17:04:08 -07:00
tangxifan 6aefa8077e [Arch] Critical patch on LE architecture which enables correct shift register connections 2020-11-25 16:40:54 -07:00
tangxifan a92b9ce482 [Arch] Test Quicklogic test architecture 2020-11-25 15:58:50 -07:00
tangxifan 55db5d5aaf [Arch] Revert to the classical pin location in vpr arch 2020-11-17 15:09:31 -07:00
tangxifan 22d0aaafeb [Arch] Move global pins to the first of pin list in vpr architecture to ease backend scripts 2020-11-17 11:47:47 -07:00
tangxifan 290b1f47a0 [Arch] Change I/O density to interface wishbone 2020-11-13 17:44:53 -07:00
tangxifan be33082faf [Arch] Remove out-of-data architectures 2020-11-13 09:50:45 -07:00
tangxifan bbf871d22a [Arch] Limit shift register chain only to columns of clbs 2020-11-13 09:39:59 -07:00
tangxifan 5d3b08ada4 [Arch] Rename ports to be consistent with backend scripts and remove shift-register chain across fabric 2020-11-13 09:24:57 -07:00
tangxifan 16af5e6ad8 [Arch] Minor change to keep a regular arch in fle->lut connection 2020-11-09 15:52:46 -07:00
tangxifan 630c4060a8 [Arch] Detect some bugs (will not cause verification failed) in vpr arch 2020-11-09 15:12:00 -07:00
tangxifan 6811604e5c [Arch] Revert back to a lower Fc for area efficiency 2020-11-05 22:23:11 -07:00
tangxifan fe3bf8ba58 [Arch] Patch to have UNIQUE routing blocks 2020-11-05 22:20:51 -07:00
tangxifan 1892dd5205 [Arch] Minor patch on arch to force unique CBY 2020-11-05 21:55:43 -07:00