| .. |
|
bitstream_manager.cpp
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
bitstream_manager.h
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
bitstream_manager_fwd.h
|
add more methods to bitstream manager (renamed from bitstream context)
|
2019-10-24 15:43:29 -06:00 |
|
bitstream_manager_utils.cpp
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
bitstream_manager_utils.h
|
fixed bugs in refactored bitstream generation
|
2019-10-26 16:40:14 -06:00 |
|
device_coordinator.cpp
|
Add copy constructor for RRChan, RRSwitchBlock etc.
|
2019-05-27 15:44:34 -06:00 |
|
device_coordinator.h
|
Add copy constructor for RRChan, RRSwitchBlock etc.
|
2019-05-27 15:44:34 -06:00 |
|
fpga_x2p_api.c
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
fpga_x2p_api.h
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
fpga_x2p_backannotate_utils.c
|
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
|
2019-06-25 21:59:38 -06:00 |
|
fpga_x2p_backannotate_utils.h
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
fpga_x2p_benchmark_utils.cpp
|
single mode is working, multi-mode is under debugging
|
2019-10-29 22:32:36 -06:00 |
|
fpga_x2p_benchmark_utils.h
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
fpga_x2p_bitstream_utils.c
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
fpga_x2p_bitstream_utils.h
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
fpga_x2p_globals.c
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
fpga_x2p_globals.h
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
|
fpga_x2p_lut_utils.c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
|
fpga_x2p_lut_utils.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
fpga_x2p_mem_utils.cpp
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
fpga_x2p_mem_utils.h
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
fpga_x2p_mux_utils.c
|
refactoring mux Verilog generation for switch blocks
|
2019-09-26 20:59:19 -06:00 |
|
fpga_x2p_mux_utils.h
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
|
fpga_x2p_naming.cpp
|
added fabric bitstream generator and fixed critical bugs in top module graph
|
2019-10-27 18:47:33 -06:00 |
|
fpga_x2p_naming.h
|
added fabric bitstream generator and fixed critical bugs in top module graph
|
2019-10-27 18:47:33 -06:00 |
|
fpga_x2p_pbtypes_utils.c
|
refactored grid bitstream generation
|
2019-10-25 21:49:47 -06:00 |
|
fpga_x2p_pbtypes_utils.h
|
refactored grid bitstream generation
|
2019-10-25 21:49:47 -06:00 |
|
fpga_x2p_reserved_words.h
|
add bitstream writers and start debugging
|
2019-10-26 12:41:23 -06:00 |
|
fpga_x2p_rr_graph_utils.c
|
many bug fixing and now start improving the routability of tileable rr_graph
|
2019-06-24 17:33:29 -06:00 |
|
fpga_x2p_rr_graph_utils.h
|
many bug fixing and now start improving the routability of tileable rr_graph
|
2019-06-24 17:33:29 -06:00 |
|
fpga_x2p_setup.c
|
critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
|
fpga_x2p_setup.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
fpga_x2p_timing_utils.c
|
developed new rotating methods for RRSwitchBlocks, debugging ongoing
|
2019-05-26 23:35:30 -06:00 |
|
fpga_x2p_timing_utils.h
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
fpga_x2p_types.h
|
refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
fpga_x2p_unique_routing.c
|
critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
|
fpga_x2p_unique_routing.h
|
critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
|
fpga_x2p_utils.c
|
start adding memory circuit to Switch blocks
|
2019-09-27 18:08:37 -06:00 |
|
fpga_x2p_utils.h
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
link_arch_circuit_lib.cpp
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
link_arch_circuit_lib.h
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
module_manager.cpp
|
add configurable child list to module manager
|
2019-10-23 15:44:13 -06:00 |
|
module_manager.h
|
add configurable child list to module manager
|
2019-10-23 15:44:13 -06:00 |
|
module_manager_fwd.h
|
plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
|
2019-10-21 00:00:30 -06:00 |
|
module_manager_utils.cpp
|
bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
|
2019-11-04 18:05:50 -07:00 |
|
module_manager_utils.h
|
bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
|
2019-11-04 18:05:50 -07:00 |
|
netlist_manager.cpp
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
netlist_manager.h
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
netlist_manager_fwd.h
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
quicksort.c
|
upgrade Verilog SB generator using the RRSwitchBlock
|
2019-05-23 17:37:39 -06:00 |
|
quicksort.h
|
upgrade Verilog SB generator using the RRSwitchBlock
|
2019-05-23 17:37:39 -06:00 |
|
rr_blocks.cpp
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
rr_blocks.h
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
rr_blocks_naming.cpp
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
|
rr_blocks_naming.h
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
|
rr_blocks_utils.cpp
|
refactored shared config bits calculation
|
2019-10-06 16:57:53 -06:00 |
|
rr_blocks_utils.h
|
refactored shared config bits calculation
|
2019-10-06 16:57:53 -06:00 |
|
simulation_utils.cpp
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
|
simulation_utils.h
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
|
write_rr_blocks.cpp
|
fixed the bug in determine passing wires for rr_gsb
|
2019-06-26 10:50:23 -06:00 |
|
write_rr_blocks.h
|
update rr_block writer to include IPINs in XML files
|
2019-06-25 11:17:22 -06:00 |
5d507ae8ee