224 lines
15 KiB
C++
224 lines
15 KiB
C++
/******************************************************************************
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* This files includes data structures for module management.
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* It keeps a list of modules that have been generated, the port map of the modules,
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* parents and children of each modules. This will ease instanciation of modules
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* with explicit port map and outputting a hierarchy of modules
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*
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* Module includes the basic information:
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* 1. unique identifier
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* 2. module name: which should be unique
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* 3. port list: basic information of all the ports belonging to the module
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* 4. port types: types of each port, which will matter how we output the ports
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* 5. parent modules: ids of parent modules
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* 6. children modules: ids of child modules
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******************************************************************************/
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#ifndef MODULE_MANAGER_H
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#define MODULE_MANAGER_H
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#include <string>
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#include <map>
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#include "vtr_vector.h"
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#include "module_manager_fwd.h"
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#include "device_port.h"
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class ModuleManager {
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public: /* Private data structures */
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enum e_module_port_type {
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MODULE_GLOBAL_PORT, /* Global inputs */
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MODULE_GPIO_PORT, /* General-purpose IOs, which are data IOs of the fabric */
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MODULE_INOUT_PORT, /* Normal (non-global) inout ports */
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MODULE_INPUT_PORT, /* Normal (non-global) input ports */
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MODULE_OUTPUT_PORT, /* Normal (non-global) output ports */
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MODULE_CLOCK_PORT, /* Nromal (non-global) clock ports*/
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NUM_MODULE_PORT_TYPES
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};
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public: /* Public Constructors */
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public: /* Types and ranges */
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typedef vtr::vector<ModuleId, ModuleId>::const_iterator module_iterator;
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typedef vtr::vector<ModulePortId, ModulePortId>::const_iterator module_port_iterator;
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typedef vtr::vector<ModuleNetId, ModuleNetId>::const_iterator module_net_iterator;
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typedef vtr::vector<ModuleNetSrcId, ModuleNetSrcId>::const_iterator module_net_src_iterator;
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typedef vtr::vector<ModuleNetSinkId, ModuleNetSinkId>::const_iterator module_net_sink_iterator;
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typedef vtr::Range<module_iterator> module_range;
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typedef vtr::Range<module_port_iterator> module_port_range;
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typedef vtr::Range<module_net_iterator> module_net_range;
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typedef vtr::Range<module_net_src_iterator> module_net_src_range;
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typedef vtr::Range<module_net_sink_iterator> module_net_sink_range;
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public: /* Public aggregators */
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/* Find all the modules */
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module_range modules() const;
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/* Find all the ports belonging to a module */
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module_port_range module_ports(const ModuleId& module) const;
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/* Find all the nets belonging to a module */
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module_net_range module_nets(const ModuleId& module) const;
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/* Find all the child modules under a parent module */
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std::vector<ModuleId> child_modules(const ModuleId& parent_module) const;
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/* Find all the instances under a parent module */
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std::vector<size_t> child_module_instances(const ModuleId& parent_module, const ModuleId& child_module) const;
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/* Find all the configurable child modules under a parent module */
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std::vector<ModuleId> configurable_children(const ModuleId& parent_module) const;
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/* Find all the instances of configurable child modules under a parent module */
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std::vector<size_t> configurable_child_instances(const ModuleId& parent_module) const;
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/* Find the source ids of modules */
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module_net_src_range module_net_sources(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the sink ids of modules */
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module_net_sink_range module_net_sinks(const ModuleId& module, const ModuleNetId& net) const;
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public: /* Public accessors */
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size_t num_modules() const;
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size_t num_nets(const ModuleId& module) const;
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std::string module_name(const ModuleId& module_id) const;
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std::string module_port_type_str(const enum e_module_port_type& port_type) const;
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std::vector<BasicPort> module_ports_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;
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std::vector<ModulePortId> module_port_ids_by_type(const ModuleId& module_id, const enum e_module_port_type& port_type) const;
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/* Find a port of a module by a given name */
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ModulePortId find_module_port(const ModuleId& module_id, const std::string& port_name) const;
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/* Find the Port information with a given port id */
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BasicPort module_port(const ModuleId& module_id, const ModulePortId& port_id) const;
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/* Find a module by a given name */
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ModuleId find_module(const std::string& name) const;
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/* Find the number of instances of a child module in the parent module */
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size_t num_instance(const ModuleId& parent_module, const ModuleId& child_module) const;
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/* Find the instance name of a child module */
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std::string instance_name(const ModuleId& parent_module, const ModuleId& child_module,
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const size_t& instance_id) const;
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/* Find the instance id of a given instance name */
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size_t instance_id(const ModuleId& parent_module, const ModuleId& child_module,
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const std::string& instance_name) const;
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/* Find if a port is a wire connection */
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bool port_is_wire(const ModuleId& module, const ModulePortId& port) const;
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/* Find if a port is register */
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bool port_is_register(const ModuleId& module, const ModulePortId& port) const;
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/* Return the pre-processing flag of a port */
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std::string port_preproc_flag(const ModuleId& module, const ModulePortId& port) const;
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/* Find a net from an instance of a module */
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ModuleNetId module_instance_port_net(const ModuleId& parent_module,
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const ModuleId& child_module, const size_t& child_instance,
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const ModulePortId& child_port, const size_t& child_pin) const;
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/* Find the name of net */
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std::string net_name(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the source modules of a net */
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vtr::vector<ModuleNetSrcId, ModuleId> net_source_modules(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the ids of source instances of a net */
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vtr::vector<ModuleNetSrcId, size_t> net_source_instances(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the source ports of a net */
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vtr::vector<ModuleNetSrcId, ModulePortId> net_source_ports(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the source pin indices of a net */
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vtr::vector<ModuleNetSrcId, size_t> net_source_pins(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the sink modules of a net */
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vtr::vector<ModuleNetSinkId, ModuleId> net_sink_modules(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the ids of sink instances of a net */
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vtr::vector<ModuleNetSinkId, size_t> net_sink_instances(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the sink ports of a net */
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vtr::vector<ModuleNetSinkId, ModulePortId> net_sink_ports(const ModuleId& module, const ModuleNetId& net) const;
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/* Find the sink pin indices of a net */
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vtr::vector<ModuleNetSinkId, size_t> net_sink_pins(const ModuleId& module, const ModuleNetId& net) const;
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private: /* Private accessors */
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size_t find_child_module_index_in_parent_module(const ModuleId& parent_module, const ModuleId& child_module) const;
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public: /* Public mutators */
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/* Add a module */
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ModuleId add_module(const std::string& name);
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/* Add a port to a module */
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ModulePortId add_port(const ModuleId& module,
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const BasicPort& port_info, const enum e_module_port_type& port_type);
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/* Set a name for a module */
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void set_module_name(const ModuleId& module, const std::string& name);
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/* Set a port to be a wire */
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void set_port_is_wire(const ModuleId& module, const std::string& port_name, const bool& is_wire);
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/* Set a port to be a register */
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void set_port_is_register(const ModuleId& module, const std::string& port_name, const bool& is_register);
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/* Set the preprocessing flag for a port */
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void set_port_preproc_flag(const ModuleId& module, const ModulePortId& port, const std::string& preproc_flag);
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/* Add a child module to a parent module */
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void add_child_module(const ModuleId& parent_module, const ModuleId& child_module);
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/* Set the instance name of a child module */
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void set_child_instance_name(const ModuleId& parent_module, const ModuleId& child_module, const size_t& instance_id, const std::string& instance_name);
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/* Add a configurable child module to module */
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void add_configurable_child(const ModuleId& module, const ModuleId& child_module, const size_t& child_instance);
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/* Add a net to the connection graph of the module */
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ModuleNetId create_module_net(const ModuleId& module);
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/* Set the name of net */
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void set_net_name(const ModuleId& module, const ModuleNetId& net,
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const std::string& name);
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/* Add a source to a net in the connection graph */
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ModuleNetSrcId add_module_net_source(const ModuleId& module, const ModuleNetId& net,
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const ModuleId& src_module, const size_t& instance_id,
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const ModulePortId& src_port, const size_t& src_pin);
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/* Add a sink to a net in the connection graph */
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ModuleNetSinkId add_module_net_sink(const ModuleId& module, const ModuleNetId& net,
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const ModuleId& sink_module, const size_t& instance_id,
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const ModulePortId& sink_port, const size_t& sink_pin);
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public: /* Public validators/invalidators */
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bool valid_module_id(const ModuleId& module) const;
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bool valid_module_port_id(const ModuleId& module, const ModulePortId& port) const;
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bool valid_module_net_id(const ModuleId& module, const ModuleNetId& net) const;
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private: /* Private validators/invalidators */
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void invalidate_name2id_map();
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void invalidate_port_lookup();
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void invalidate_net_lookup();
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private: /* Internal data */
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/* Module-level data */
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vtr::vector<ModuleId, ModuleId> ids_; /* Unique identifier for each Module */
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vtr::vector<ModuleId, std::string> names_; /* Unique identifier for each Module */
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vtr::vector<ModuleId, std::vector<ModuleId>> parents_; /* Parent modules that include the module */
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vtr::vector<ModuleId, std::vector<ModuleId>> children_; /* Child modules that this module contain */
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vtr::vector<ModuleId, std::vector<size_t>> num_child_instances_; /* Number of children instance in each child module */
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vtr::vector<ModuleId, std::vector<std::vector<std::string>>> child_instance_names_; /* Number of children instance in each child module */
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/* Configurable child modules are used to record the position of configurable modules in bitstream
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* The sequence of children in the list denotes which one is configured first, etc.
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* Note that the sequence can be totally different from the children_ list
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* This is really dependent how the configuration protocol is organized
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* which should be made by users/designers
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*/
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vtr::vector<ModuleId, std::vector<ModuleId>> configurable_children_; /* Child modules with configurable memory bits that this module contain */
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vtr::vector<ModuleId, std::vector<size_t>> configurable_child_instances_; /* Instances of child modules with configurable memory bits that this module contain */
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/* Port-level data */
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vtr::vector<ModuleId, vtr::vector<ModulePortId, ModulePortId>> port_ids_; /* List of ports for each Module */
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vtr::vector<ModuleId, vtr::vector<ModulePortId, BasicPort>> ports_; /* List of ports for each Module */
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vtr::vector<ModuleId, vtr::vector<ModulePortId, enum e_module_port_type>> port_types_; /* Type of ports */
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vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>> port_is_wire_; /* If the port is a wire, use for Verilog port definition. If enabled: <port_type> reg <port_name> */
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vtr::vector<ModuleId, vtr::vector<ModulePortId, bool>> port_is_register_; /* If the port is a register, use for Verilog port definition. If enabled: <port_type> reg <port_name> */
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vtr::vector<ModuleId, vtr::vector<ModulePortId, std::string>> port_preproc_flags_; /* If a port is available only when a pre-processing flag is enabled. This is to record the pre-processing flags */
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/* Graph-level data:
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* We use nets to model the connection between pins of modules and instances.
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* To avoid large memory footprint, we do NOT create pins,
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* To enable fast look-up on pins, we create a fast look-up
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*/
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, ModuleNetId>> net_ids_; /* List of nets for each Module */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, std::string>> net_names_; /* Name of net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, ModuleNetSrcId>>> net_src_ids_; /* Unique id of the source that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, ModuleId>>> net_src_module_ids_; /* Pin ids that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, size_t>>> net_src_instance_ids_; /* Pin ids that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, ModulePortId>>> net_src_port_ids_; /* Pin ids that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSrcId, size_t>>> net_src_pin_ids_; /* Pin ids that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, ModuleNetSinkId>>> net_sink_ids_; /* Unique ids of the sink that the net drives */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, ModuleId>>> net_sink_module_ids_; /* Pin ids that the net drives */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, size_t>>> net_sink_instance_ids_; /* Pin ids that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, ModulePortId>>> net_sink_port_ids_; /* Pin ids that drive the net */
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vtr::vector<ModuleId, vtr::vector<ModuleNetId, vtr::vector<ModuleNetSinkId, size_t>>> net_sink_pin_ids_; /* Pin ids that drive the net */
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/* fast look-up for module */
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std::map<std::string, ModuleId> name_id_map_;
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/* fast look-up for ports */
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typedef vtr::vector<ModuleId, std::vector<std::vector<ModulePortId>>> PortLookup;
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mutable PortLookup port_lookup_; /* [module_ids][port_types][port_ids] */
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/* fast look-up for nets */
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typedef vtr::vector<ModuleId, std::map<ModuleId, std::vector<std::map<ModulePortId, std::vector<ModuleNetId>>>>> NetLookup;
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mutable NetLookup net_lookup_; /* [module_ids][module_ids][instance_ids][port_ids][pin_ids] */
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};
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#endif
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