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FIR_filter
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[Benchmark] Add micro benchmark for FIR filter
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2021-02-18 19:37:44 -07:00 |
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FSM_three_code
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enrich micro benchmarks
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2020-07-22 12:33:52 -06:00 |
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RISC_posedge_clk
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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SAPone
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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adder
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[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
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2021-06-30 15:29:13 -06:00 |
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and2
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
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and2_latch
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
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and2_latch_2clock
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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and2_or2
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[Benchmark] Bug fix in the and2_or2 benchmark
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2020-09-17 10:35:13 -06:00 |
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and2_pipelined
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[Benchmark] Bug fix in pipelined and2 benchmark
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2021-01-10 10:27:59 -07:00 |
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and4
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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asyn_spram_4x1
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Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
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2021-01-29 10:19:05 -07:00 |
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blinking
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[Benchmark] Add microbenchmark 1-bit blinking
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2021-05-06 15:17:27 -06:00 |
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clk_divider
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[benchmark] add clock divider
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2023-01-13 16:39:06 -08:00 |
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clk_gate
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[test] fixed a few bugs
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2022-09-29 15:32:31 -07:00 |
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config_loader
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
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counters
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[hdl] add a counter design which is triggered by negative edges
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2022-05-09 16:41:21 +08:00 |
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discrete_dffn
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[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
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2023-01-15 13:09:40 -08:00 |
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dual_port_ram_1k
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[Benchmark] Add 1k DPRAM benchmark which can fit new arch
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2021-04-28 11:26:31 -06:00 |
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dual_port_ram_16k
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[Benchmark] Bug fix in dual port ram 16k benchmark
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2021-04-27 23:33:20 -06:00 |
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fifo/rtl
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[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
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2021-04-27 22:09:10 -06:00 |
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mac
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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mult
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[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
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or2
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
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pipelined_8bit_adder
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[Benchmark] move benchmarks to microbenchmark category
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2021-04-27 22:12:30 -06:00 |
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routing_test
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bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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rst_on_lut
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[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
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2022-09-12 10:43:21 -07:00 |
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rst_on_lut_4bit
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[test] deploy new benchmarks
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2024-06-02 14:23:08 -07:00 |
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rst_on_lut_8bit
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[test] add and deploy new benchmark
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2024-06-02 14:27:02 -07:00 |
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signal_gen
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fixed tab spacing
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2021-07-01 16:42:04 -06:00 |
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syn_spram_4x1
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Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
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2021-01-29 10:19:05 -07:00 |
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test_mode_low
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Added test_mode_low benchmark
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2020-06-11 19:31:01 -06:00 |
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test_modes
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[Benchmark] move benchmarks to microbenchmark category
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2021-04-27 22:12:30 -06:00 |
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two_dff_inv_rst
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[benchmark] syntax
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2023-01-18 18:34:24 -08:00 |
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