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dpram1K_dsp18_fracff_cell_sim.v
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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dsp_map.v
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
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[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
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2021-03-23 15:30:41 -06:00 |
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k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
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[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
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2021-03-23 15:30:41 -06:00 |
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k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v
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[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
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2021-04-24 13:30:46 -06:00 |
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k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v
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[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
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2021-04-24 13:30:46 -06:00 |
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
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[HDL] Rename tech lib to be consistent with arch name changes
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2021-03-20 18:08:03 -06:00 |
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_cell_sim.v
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[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm_dff_map.v
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[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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mem1K_bram.txt
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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mem1K_bram_map.v
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started updating timings
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2021-07-19 10:48:55 -06:00 |
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openfpga_adders_sim.v
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[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
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2021-03-16 18:04:31 -06:00 |
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openfpga_arith_map.v
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[Script] Rename yosys script supporting bram and restructure techlib files
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2021-03-16 16:16:53 -06:00 |
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openfpga_brams.txt
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[Script] Rename yosys script supporting bram and restructure techlib files
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2021-03-16 16:16:53 -06:00 |
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openfpga_brams_map.v
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[Script] Rename yosys script supporting bram and restructure techlib files
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2021-03-16 16:16:53 -06:00 |
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openfpga_brams_sim.v
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[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
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2021-03-17 15:09:12 -06:00 |
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openfpga_dff_map.v
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[Script] Add dff with active-low async reset to default yosys tech lib
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2021-07-02 11:17:43 -06:00 |
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openfpga_dff_sim.v
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[Script] Add dff with active-low async reset to default yosys tech lib
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2021-07-02 11:17:43 -06:00 |
