Andrew Pond 6cb51d1e7d timing files renamed		2021-07-21 14:12:32 -06:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	Merge branch 'master' into bram_changes	2021-07-06 15:33:40 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	timing files renamed	2021-07-21 14:12:32 -06:00
openfpga_arch	started updating timings	2021-07-19 10:48:55 -06:00
openfpga_cell_library	[HDL] Added a multi-mode FF design with configurable asynchronous reset	2021-07-02 11:13:03 -06:00
openfpga_shell_scripts	started modifying arch files	2021-07-16 09:09:25 -06:00
openfpga_simulation_settings	[Arch] Add simulation setting for 8-clock architectures	2021-02-22 11:10:03 -07:00
openfpga_timing_annotation	timing files renamed	2021-07-21 14:12:32 -06:00
openfpga_yosys_techlib	started updating timings	2021-07-19 10:48:55 -06:00
regression_test_scripts	Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench	2021-07-01 15:29:39 -06:00
scripts	[Script] Patching the run_fpga_task.py on pin constraint files	2021-07-02 15:59:29 -06:00
tasks	Merge branch 'master' into bram_changes	2021-07-06 15:33:40 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	timing files renamed	2021-07-21 14:12:32 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00