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formality_template.tcl
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Updated formality python script
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2019-09-27 14:00:57 -06:00 |
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fpgaflow_default_tool_path.conf
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[Script] Update default list of result extraction for openfpga flow
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2021-03-23 11:06:42 -06:00 |
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modelsim_proc.tcl
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Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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modelsim_runsim.tcl
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Fixed modelsim include references
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2020-06-11 19:28:13 -06:00 |
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qlf_yosys.ys
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[Script] Update quicklogic's script to output correct verilog file name
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2021-03-08 21:39:44 -07:00 |
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ys_tmpl_rewrite_flow.ys
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[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
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2021-03-10 13:56:35 -07:00 |
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ys_tmpl_yosys_vpr_bram_dff_flow.ys
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timing files renamed
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2021-07-21 14:12:32 -06:00 |
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ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
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pmux2mux.v path change
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2021-07-06 12:25:51 -06:00 |
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ys_tmpl_yosys_vpr_bram_dsp_flow.ys
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pmux2mux yosys script change
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2021-07-06 14:19:28 -06:00 |
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ys_tmpl_yosys_vpr_bram_flow.ys
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[Script] Update yosys script using BRAMs
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2021-04-27 21:44:27 -06:00 |
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ys_tmpl_yosys_vpr_dff_flow.ys
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[Script] Patch yosys script with dff tech map
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2021-04-16 20:47:18 -06:00 |
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ys_tmpl_yosys_vpr_dsp_dff_flow.ys
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removed duplicate yosys script
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2021-07-21 08:09:20 -06:00 |
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ys_tmpl_yosys_vpr_dsp_flow.ys
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[Script] Add a template yosys script support only DSP mapping
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2021-03-23 15:32:10 -06:00 |
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ys_tmpl_yosys_vpr_flow.ys
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Added fpga_flow script - Working Yosys
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2019-08-09 16:49:05 -06:00 |
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ys_tmpl_yosys_vpr_flow_with_rewrite.ys
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[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
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2021-03-10 13:56:35 -07:00 |
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