tangxifan 958ef37a83 Merge pull request #864 from yunuseryilmaz18/master ... Update dpram16k.v, dpram_2048x8.v, and dpram1k.v		2022-10-30 12:16:21 -07:00
..
adder.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
aib.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
buf4.v	bugfix in alt	2021-02-08 23:04:00 -05:00
dff.v	[arch] add arch that supports negative edge triggered flip-flop	2022-05-09 16:32:01 +08:00
dpram.v	Update dpram.v	2022-10-27 08:29:56 +03:00
dpram1k.v	Update dpram1k.v	2022-10-26 16:32:14 +03:00
dpram8k.v	[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells	2021-03-17 15:15:22 -06:00
dpram16k.v	Update dpram16k.v	2022-10-27 08:28:58 +03:00
dpram_2048x8.v	Update dpram_2048x8.v	2022-10-26 16:31:16 +03:00
frac_lut4_arith.v	[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]	2021-03-11 15:23:14 -07:00
frac_mem_32k.v	Update frac_mem_32k.v	2022-10-20 09:48:29 +03:00
frac_mult_16x16.v	[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block	2021-04-24 14:57:09 -06:00
frac_mult_36x36.v	Added new cell library for fracturable dsp36	2022-10-21 17:30:20 +03:00
gpio.v	[Test] Update test case by using GPIO with config_done signals	2022-02-24 09:49:34 -08:00
inv.v	adding dff synth	2021-02-09 10:34:54 -05:00
latch.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
lut6.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
mult_8x8.v	[HDL] Add HDL for 8-bit single-mode multiplier	2021-03-23 15:36:09 -06:00
mult_32x32.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
mult_36x36.v	[Architecture] Reorganize the cell netlists and update architecture files accordingly	2020-09-25 11:55:28 -06:00
mux2.v	[HDL] Bug fix in HDL netlist due to port name mismatching	2021-02-01 11:35:25 -07:00
or2.v	no need for dff*, but need tap_buf4	2021-02-08 23:00:13 -05:00
spram_4x1.v	Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)	2021-01-29 10:19:05 -07:00
sram.v	[HDL] Temporarily disable WLR func in primitive HDL modeling	2021-09-20 17:07:51 -07:00
tap_buf4.v	no need for dff*, but need tap_buf4	2021-02-08 22:27:57 -05:00