Ganesh Gore 4f6b8c0905 Updated regression tests		2023-02-11 22:11:06 -07:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[test] adding a new test case to validate the bitstream overloading for DSP blocks	2023-01-24 14:58:52 -08:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	[script] wrong path to yosys bin	2023-02-03 22:54:22 -08:00
openfpga_arch	[arch] comment on the wrong mode bits	2023-01-24 15:24:17 -08:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs	2023-01-18 18:31:36 -08:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[arch] adding tech lib;	2023-01-24 15:22:34 -08:00
regression_test_scripts	Updated regression tests	2023-02-11 22:11:06 -07:00
scripts	Updated format	2023-02-11 18:12:04 -07:00
tasks	renamed yosys_vpr_template fabric_netlist_gen_template	2023-02-11 18:33:06 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[test] debugging	2023-01-24 17:57:34 -08:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00