57 lines
977 B
Verilog
57 lines
977 B
Verilog
//-----------------------------------------------------
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// Design Name : dual_port_ram
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// File Name : dpram.v
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// Function : Dual port RAM 32x1024
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// Coder : Aurelien
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//-----------------------------------------------------
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module dpram_512x32 (
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input clk,
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input wen,
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input ren,
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input[0:8] waddr,
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input[0:8] raddr,
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input[0:31] d_in,
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output[0:31] d_out );
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dpram_512x32_core memory_0 (
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.wclk (clk),
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.wen (wen),
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.waddr (waddr),
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.data_in (d_in),
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.rclk (clk),
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.ren (ren),
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.raddr (raddr),
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.d_out (d_out) );
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endmodule
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module dpram_512x32_core (
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input wclk,
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input wen,
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input[0:8] waddr,
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input[0:31] data_in,
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input rclk,
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input ren,
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input[0:8] raddr,
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output[0:31] d_out );
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reg[0:31] ram[0:511];
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reg[0:31] internal;
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assign d_out = internal;
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always @(posedge wclk) begin
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if(wen) begin
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ram[waddr] <= data_in;
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end
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end
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always @(posedge rclk) begin
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if(ren) begin
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internal <= ram[raddr];
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end
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end
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endmodule
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