599 lines
15 KiB
Verilog
599 lines
15 KiB
Verilog
//-----------------------------------------------------
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// Design Name : D-type Flip-flops
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// File Name : ff.v
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//-----------------------------------------------------
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// Function : A native D-type flip-flop with single output
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//-----------------------------------------------------
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module DFFQ (
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input CK, // Clock Input
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input D, // Data Input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ (posedge CK) begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : A native D-type flip-flop
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//-----------------------------------------------------
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module DFF (
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ (posedge CK) begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = ~q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - single output
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// - asynchronous active high reset
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//-----------------------------------------------------
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module DFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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//-----------------------------------------------------
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module DFFR (
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = ~q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active low reset
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//-----------------------------------------------------
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module DFFRN (
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input RSTN, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or negedge RSTN)
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if (~RSTN) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = ~q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high set
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//-----------------------------------------------------
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module DFFS (
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input SET, // Set input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge SET)
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if (SET) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = ~q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active low set
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//-----------------------------------------------------
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module DFFSN (
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input SETN, // Set input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or negedge SETN)
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if (~SETN) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = ~q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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//-----------------------------------------------------
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module DFFSR (
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input SET, // set input
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = ~q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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//-----------------------------------------------------
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module DFFSRQ (
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input SET, // set input
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : A multi-functional D-type flip-flop with
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// - asynchronous reset
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// which can be switched between active-low and active high
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// - asynchronous set
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// which can be switched between active-low and active high
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//-----------------------------------------------------
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module MULTI_MODE_DFFSRQ (
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input SET, // Set input
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
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);
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wire post_set = mode[1] ? ~SET : SET;
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wire post_rst = mode[0] ? ~RST : RST;
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DFFSRQ FF_CORE (.SET(post_set),
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.RST(post_rst),
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.CK(CK),
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.D(D),
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.Q(Q)
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);
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : A multi-functional D-type flip-flop with
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// - asynchronous reset
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// which can be switched between active-low and active high
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//-----------------------------------------------------
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module MULTI_MODE_DFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
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);
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wire post_rst = mode ? ~RST : RST;
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DFFRQ FF_CORE (.RST(post_rst),
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.CK(CK),
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.D(D),
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.Q(Q)
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);
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : A multi-functional D-type flip-flop with
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// - asynchronous reset
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// which can be switched between active-low and active high
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// - clock
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// which can be switched between positive edge triggered and negative edge triggered
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//-----------------------------------------------------
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module MULTI_MODE_DFFNRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
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);
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wire post_rst = mode[0] ? ~RST : RST;
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wire post_clk = mode[1] ? ~CK : CK;
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DFFRQ FF_CORE (.RST(post_rst),
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.CK(post_clk),
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.D(D),
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.Q(Q)
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);
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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// - scan-chain input
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// - a scan-chain enable
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//-----------------------------------------------------
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module SDFFSR (
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input SET, // Set input
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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output Q, // Q output
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output QN // Q negative output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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assign QN = !Q;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - scan-chain input
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// - a scan-chain enable
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//-----------------------------------------------------
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module SDFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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// - scan-chain input
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// - a scan-chain enable
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//-----------------------------------------------------
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module SDFFSRQ (
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input SET, // Set input
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - scan-chain input
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// - a scan-chain enable
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// - a configure enable, when enabled the registered output will
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// be released to the Q
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//-----------------------------------------------------
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module CFGSDFFR (
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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input CFGE, // Configure enable
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output Q, // Regular Q output
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output CFGQ, // Data Q output which is released when configure enable is activated
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output CFGQN // Data Qb output which is released when configure enable is activated
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);
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//------------Internal Variables--------
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reg q_reg;
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wire QN;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign CFGQ = CFGE ? Q : 1'b0;
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assign CFGQN = CFGE ? QN : 1'b1;
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assign Q = q_reg;
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assign QN = !Q;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - scan-chain input
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// - a scan-chain enable
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// - a configure enable, when enabled the registered output will
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// be released to the CFGQ
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// - a configure done, when enable, the regsitered output will be released to the Q
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//-----------------------------------------------------
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module CFGDSDFFR (
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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input CFGE, // Configure enable
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input CFG_DONE, // Configure done
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output Q, // Regular Q output
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output CFGQ, // Data Q output which is released when configure enable is activated
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output CFGQN // Data Qb output which is released when configure enable is activated
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);
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//------------Internal Variables--------
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reg q_reg;
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wire QN;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign CFGQ = CFGE ? Q : 1'b0;
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assign CFGQN = CFGE ? QN : 1'b1;
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assign Q = CFG_DONE ? q_reg : 1'b0;
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assign QN = CFG_DONE ? !Q : 1'b1;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// @note This DFF is designed to drive BLs when shift registers are used
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//-----------------------------------------------------
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module BL_DFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input SIN, // Data Input
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output SOUT, // Q output
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output BL // BL output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= SIN;
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end
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assign SOUT = q_reg;
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assign BL = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// @note This DFF is designed to drive WLs when shift registers are used
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//-----------------------------------------------------
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module WL_DFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input SIN, // Data Input
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input WEN, // Write-enable
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output SOUT, // Q output
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output WLW // Drive WL write signals
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= SIN;
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end
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assign SOUT = q_reg;
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assign WLW = WEN ? q_reg : 1'b0;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// @note This DFF is designed to drive WLs and WLRs when shift registers are used
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//-----------------------------------------------------
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module WLR_DFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input SIN, // Data Input
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input WEN, // Write-enable
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output SOUT, // Q output
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output WLW, // Drive WL write signals
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output WLR // Drive WL read signals
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= SIN;
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end
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assign SOUT = q_reg;
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assign WLW = WEN ? q_reg : 1'b0;
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assign WLR = 1'b0; // Use a constant output just for simple testing
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endmodule //End Of Module
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