36 lines
1017 B
Verilog
36 lines
1017 B
Verilog
//-----------------------------------------------------
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// Design Name : mult_36x36
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// File Name : mult_36x36.v
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// Function : A 36-bit multiplier which can operate in fracturable modes:
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// 1. four 9-bit multipliers
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// 2. two 18-bit multipliers
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// 3. one 36-bit multipliers
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// Coder : Xifan Tang
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//-----------------------------------------------------
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module mult_36x36 (
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input [0:35] a,
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input [0:35] b,
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output [0:71] out,
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input [0:1] mode);
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reg [0:71] out_reg;
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always @(mode, a, b) begin
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if (2'b01 == mode) begin
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out_reg[0:17] <= a[0:8] * b[0:8];
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out_reg[18:35] <= a[9:17] * b[9:17];
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out_reg[36:53] <= a[18:26] * b[18:26];
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out_reg[54:71] <= a[27:35] * b[27:35];
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end else if (2'b10 == mode) begin
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out_reg[0:35] <= a[0:17] * b[0:17];
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out_reg[36:71] <= a[18:35] * b[18:35];
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end else begin
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out_reg <= a * b;
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end
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end
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assign out = out_reg;
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endmodule
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