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basic_command.cpp
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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basic_command.h
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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io_location_map.cpp
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build io location map
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2020-02-26 19:58:18 -07:00 |
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io_location_map.h
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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openfpga_bitstream.cpp
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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openfpga_bitstream.h
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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openfpga_bitstream_command.cpp
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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openfpga_bitstream_command.h
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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openfpga_build_fabric.cpp
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build io location map
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2020-02-26 19:58:18 -07:00 |
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openfpga_build_fabric.h
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build io location map
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2020-02-26 19:58:18 -07:00 |
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openfpga_context.h
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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openfpga_flow_manager.cpp
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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openfpga_flow_manager.h
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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openfpga_interconnect_types.h
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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openfpga_link_arch.cpp
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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openfpga_link_arch.h
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add verbose output option for openfpga linking architecture
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2020-01-31 11:36:58 -07:00 |
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openfpga_lut_truth_table_fixup.cpp
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bug fixed for lut truth table fixup. Results look good
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2020-02-06 17:47:25 -07:00 |
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openfpga_lut_truth_table_fixup.h
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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openfpga_naming.cpp
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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openfpga_naming.h
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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openfpga_pb_pin_fixup.cpp
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bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |
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openfpga_pb_pin_fixup.h
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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openfpga_read_arch.cpp
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add write_openfpga_arch command to openfpga shell
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2020-01-23 20:58:15 -07:00 |
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openfpga_read_arch.h
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add write_openfpga_arch command to openfpga shell
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2020-01-23 20:58:15 -07:00 |
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openfpga_repack.cpp
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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openfpga_repack.h
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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openfpga_reserved_words.h
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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openfpga_sdc.cpp
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use user defined critical path delay in SDC generation
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2020-02-28 11:24:39 -07:00 |
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openfpga_sdc.h
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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openfpga_sdc_command.cpp
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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openfpga_sdc_command.h
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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openfpga_setup_command.cpp
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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openfpga_setup_command.h
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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openfpga_title.cpp
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update title page
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2020-01-24 17:00:53 -07:00 |
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openfpga_title.h
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start split workload from the main.cpp in openfpga
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2020-01-23 13:24:35 -07:00 |
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openfpga_verilog.cpp
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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openfpga_verilog.h
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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openfpga_verilog_command.cpp
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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openfpga_verilog_command.h
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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