tangxifan
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82cf7bbb8c
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[core] Add verbose mode on find_node() for clock rr graph
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2024-08-02 17:47:41 -07:00 |
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tangxifan
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ae1100ceba
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[core] cleanup debug message
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2024-08-02 17:05:59 -07:00 |
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tangxifan
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ad38b52a23
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[lib] code format
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2024-08-02 12:41:00 -07:00 |
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tangxifan
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1a13c5f815
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[lib] now fabric key assistant can cross-check mismatches between reference and input fabric keys
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2024-08-02 12:31:55 -07:00 |
chungshien-chai
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766df0a1b5
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Improve Port Parser
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2024-07-31 12:19:30 -07:00 |
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chungshien-chai
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0d9f1a3c6b
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Forward searching the config bit + some minor refactor
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2024-07-28 19:12:34 -07:00 |
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chungshien-chai
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9882394c8b
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Use archfpga_throw
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2024-07-28 02:53:18 -07:00 |
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chungshien-chai
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2a3d69aded
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Update code based on feedback
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2024-07-28 02:37:15 -07:00 |
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chungshien-chai
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933155b08f
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Update test flow
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2024-07-27 23:52:54 -07:00 |
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chungshien-chai
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e60777d23e
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Use Bitstream Setting XML
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2024-07-26 01:36:49 -07:00 |
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tangxifan
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c96f899c53
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[core] code format
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2024-07-10 15:07:26 -07:00 |
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tangxifan
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a4538fb25b
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[core] now supports to_pin in building clock network for internal driver
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2024-07-10 15:01:18 -07:00 |
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tangxifan
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b2fc47a12a
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[core] reworked i/o for clock network files
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2024-07-10 14:34:54 -07:00 |
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tangxifan
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079e6f2fca
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[core] add new syntax to support from_pin and to_pin for internal driver in clock network
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2024-07-10 14:28:28 -07:00 |
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tangxifan
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0f78803759
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[core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs
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2024-07-09 20:47:15 -07:00 |
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tangxifan
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578d7c8ec0
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[core] fixed a bug on region tap point identification
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2024-07-01 20:58:41 -07:00 |
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tangxifan
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73b30841a7
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[lib] typo
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2024-07-01 20:56:27 -07:00 |
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tangxifan
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60e6e27e54
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[core] fixed a bug on tap point identificatin
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2024-07-01 20:45:55 -07:00 |
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tangxifan
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a85a6f1674
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[core] code format
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2024-07-01 17:57:10 -07:00 |
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tangxifan
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70428fd969
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[lib] add sanity checks on global port name and clock network's global port name
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2024-07-01 17:56:29 -07:00 |
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tangxifan
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df23daf026
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[lib] sanity check on global port name and from pin name of tap points
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2024-07-01 17:37:16 -07:00 |
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tangxifan
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7c487eadc9
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[core] now clock network keep port info in a native data structure
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2024-07-01 16:58:23 -07:00 |
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tangxifan
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3afb92d6a5
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[core] code format
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2024-06-30 22:48:15 -07:00 |
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tangxifan
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1fd974d544
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[core] fixed a bug where clock network size cannot impact global port on top module
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2024-06-29 17:35:47 -07:00 |
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tangxifan
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34fb003911
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[core] replace width syntax with global port name
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2024-06-29 10:46:00 -07:00 |
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tangxifan
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5cfd23747b
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[core] code format
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2024-06-28 13:47:03 -07:00 |
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tangxifan
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4185235a69
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[core] now clock routing is based on tree expansion. Unused part can be disconnected
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2024-06-27 15:02:20 -07:00 |
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tangxifan
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cab649893b
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[core] update clock architecture
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2024-06-26 18:06:39 -07:00 |
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tangxifan
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59be95b227
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[core] code format
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2024-06-26 17:58:26 -07:00 |
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tangxifan
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3efa97b84e
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[core] support coordinate on clock taps
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2024-06-26 17:40:11 -07:00 |
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tangxifan
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3b25e42720
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[lib] syntax
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2024-06-26 15:51:00 -07:00 |
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tangxifan
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381a8cb535
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[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
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2024-06-26 15:41:56 -07:00 |
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tangxifan
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4640e74e7e
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[core] code format
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2024-06-25 12:25:16 -07:00 |
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tangxifan
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66af73e91e
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[lib] now accept reset and set in programmable clock network
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2024-06-25 12:24:46 -07:00 |
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tangxifan
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7bcbd8a88b
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[core] code format
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2024-06-25 11:44:50 -07:00 |
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tangxifan
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3b2c13402a
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[core] syntax
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2024-06-25 11:44:25 -07:00 |
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tangxifan
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31d4b4c402
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[core] now support add internal drivers to clock tree
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2024-06-25 11:27:22 -07:00 |
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tangxifan
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272d78eb43
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[test] add a new unit test
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2024-06-24 19:13:36 -07:00 |
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tangxifan
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22bee35fd1
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[lib] mem allocate
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2024-06-24 18:47:56 -07:00 |
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tangxifan
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36ef555dda
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[lib] add example arch for clock arch with internal drivers
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2024-06-24 18:33:47 -07:00 |
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tangxifan
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2eda2825b7
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[lib] syntax
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2024-06-24 18:28:42 -07:00 |
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tangxifan
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0c442f6238
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[lib] add syntax to support internal drivers in clock network parsers
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2024-06-24 17:54:58 -07:00 |
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tangxifan
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2193f108ee
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[core] add debugging messages
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2024-06-21 18:42:35 -07:00 |
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tangxifan
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ecd31955b1
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[core] code format
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2024-06-21 17:11:32 -07:00 |
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tangxifan
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3ddaefc2a2
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[lib] syntax
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2024-06-21 17:02:37 -07:00 |
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tangxifan
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1ab75cf76c
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[lib] now link clock arch supports tap and driver default switches
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2024-06-21 16:52:22 -07:00 |
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tangxifan
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9ccd14bf4d
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[lib] now default switch of clk ntwk is split to default_tap_switch and default_driver_switch
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2024-06-21 16:45:05 -07:00 |
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tangxifan
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ca6e2f9831
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[core] code format
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2024-05-20 13:41:35 -07:00 |
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tangxifan
|
b15e169490
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[core] fixed a bug where wire model is expected on direct connections
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2024-05-20 12:45:49 -07:00 |
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tangxifan
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9d87e99539
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[lib] typo on keywords in XML parser
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2024-05-20 11:15:43 -07:00 |