Commit Graph

282 Commits

Author SHA1 Message Date
tangxifan 926b9e9739 [core] code format 2024-05-18 12:33:19 -07:00
tangxifan 3b93bea3d1 [core] syntax 2024-05-18 12:29:38 -07:00
tangxifan be1d7517c9 [doc] rework out-of-date syntax 2024-05-17 19:25:35 -07:00
tangxifan 0d8c21ca84 [core] add new type 'part_of_cb' for tile direct connections 2024-05-17 18:59:53 -07:00
tangxifan 36d37289fe [lib] add missing header required by clang-11+ 2024-05-05 21:21:36 -07:00
tangxifan 03bea1c566 [lib] code format 2024-05-05 18:47:37 -07:00
tangxifan df3b4357fc [lib] add header to pass Gcc-12 2024-05-05 18:24:44 -07:00
chungshien dd577e37e0
LUTRAM Support (#1595)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric

* LUTRAM Support Phase 1

* Add Test

* Add more protocol checking to enable LUTRAM feature

* Move the config setting under config protocol

* Revert any changes

---------

Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
chungshien 4365d160ff
Support extracting data that is not affecting fabric bitstream (#1566)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
Victor 39a012b939 Support checking illegal pin constraint (use loc as key and update message format) 2024-03-04 12:41:19 +08:00
Victor d2a8213566 Support checking illegal pin constraint (optimize and add comments) 2024-02-28 11:23:03 +08:00
Victor f4658ee67d Support checking illegal pin constraint (Show design pins) 2024-02-27 16:50:00 +08:00
Victor 3138481df4 Support checking illegal pin constraint 2024-02-27 10:21:16 +08:00
Yitian4Debug 1d0d8c5417
Update read_xml_repack_design_constraints.cpp
code clean up
2023-12-05 10:13:53 -08:00
Yitian4Debug e6c9d22ce9
Update repack_design_constraints.h
code clean up
2023-12-05 10:10:19 -08:00
Yitian4Debug aa51b6d388
Update repack_design_constraints.h 2023-12-05 09:40:25 -08:00
Yitian4Debug 57f3b7af0f
Update repack_design_constraints.h 2023-12-05 09:38:27 -08:00
Yitian4Debug b765410300
Update repack_design_constraints.cpp 2023-12-05 09:37:56 -08:00
Yitian4Debug 7aa882f82c
Update read_xml_repack_design_constraints.cpp 2023-12-05 09:26:05 -08:00
Yitian4Debug 0e243d1c05
Update repack_design_constraints.cpp 2023-12-05 09:17:29 -08:00
Yitian4Debug d0958fc017
Update repack_design_constraints.h 2023-12-05 09:09:45 -08:00
ubuntu a50b007d72 add vtr assert 2023-12-01 03:02:52 -08:00
ubuntu 539d41f3df reformat the code 2023-11-29 17:42:13 -08:00
ubuntu 2511b79bd6 format the code 2023-11-29 02:27:53 -08:00
ubuntu 030f9d8837 changes according to code review 2023-11-29 02:12:07 -08:00
ubuntu d28f024b61 minor change 2023-11-29 01:53:18 -08:00
tangxifan 1aac6681bc
Merge branch 'master' into repack_debug 2023-11-22 10:48:59 -08:00
ubuntu ee392f1b46 add ignore_net to repackdesign constraint 2023-11-21 21:47:03 -08:00
tangxifan 93cbbf2045 [core] code format 2023-10-06 18:20:55 -07:00
tangxifan b07111497c [core] enable options in xml writers 2023-10-06 18:20:17 -07:00
tangxifan 76f446caec [core] fixed a bug 2023-09-25 21:13:11 -07:00
tangxifan 3adf81046a [core] code format 2023-09-25 17:22:26 -07:00
tangxifan 5e269e8bc4 [core] support port merging at grid modules 2023-09-25 17:21:58 -07:00
tangxifan fd99dafad7 [core] code format 2023-09-25 16:51:01 -07:00
tangxifan 96f36a96dd [core] syntax 2023-09-25 16:50:30 -07:00
tangxifan ca715f4c82 [core] developing parser to support subtile port merge 2023-09-25 16:46:34 -07:00
tangxifan 0a94763422 [lib] add module rename assistant 2023-09-22 18:16:01 -07:00
tangxifan 278b8e2409 [lib] fixed a typo which causes outputted module name XMLs carry syntax errors 2023-09-22 17:37:27 -07:00
tangxifan c6175aa514 [core] code format 2023-09-17 22:37:48 -07:00
tangxifan ef97127c63 [core] fixed some bugs in testbenches when renaming top modules 2023-09-17 22:34:00 -07:00
tangxifan 72a3c05747 [core] code format 2023-09-17 13:29:30 -07:00
tangxifan ccd4c1861b [core] developing new command to write module naming rules 2023-09-16 19:37:06 -07:00
tangxifan 37573abc22 [core] code format 2023-09-15 23:32:40 -07:00
tangxifan bc407e5d69 [core] code complete for rename modules 2023-09-15 23:22:31 -07:00
tangxifan 7913e6cc6a [lib] update tests and fixed some bugs 2023-09-15 17:38:51 -07:00
tangxifan b5cf08a3c5 [lib] add testing 2023-09-15 17:15:05 -07:00
tangxifan 74b9f673ec [lib] syntax and add missing api 2023-09-15 17:00:02 -07:00
tangxifan 636647902e [lib] developing io for module name map 2023-09-15 16:53:24 -07:00
tangxifan e5bc936144 [lib] developing io 2023-09-15 16:19:10 -07:00
tangxifan b65dda90c4 [lib] developing naming manager 2023-09-15 16:02:13 -07:00
tangxifan af67b02cca [lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules 2023-09-15 13:51:14 -07:00
tangxifan 3273728bc3 [lib] code format 2023-08-26 18:15:30 -07:00
tangxifan ac5873bac2 [lib] fixed some bugs in message show 2023-08-26 18:12:25 -07:00
tangxifan 97619fc545 [lib] add verbose output option to fabric key assistant 2023-08-26 18:07:08 -07:00
tangxifan cfaae55bda [lib] debugged fabric key assistant 2023-08-26 13:19:18 -07:00
tangxifan adae7392e5 [lib] developing fabric key assistant 2023-08-26 12:54:12 -07:00
tangxifan d3895c3dc0 [core] code format 2023-08-03 17:34:25 -07:00
tangxifan 53050b94ab [core] developing memory group modules in grid modules 2023-08-01 17:50:03 -07:00
tangxifan 23643f3fb1 [core] developing the physical memory block builder 2023-07-31 22:57:26 -07:00
tangxifan 95a32628ab [core] fixed the bug in arch bitgen due to the tile modules 2023-07-25 14:15:15 -07:00
tangxifan 7783229d90 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile 2023-07-23 20:44:50 -07:00
tangxifan 6607bb7e48 [core] now fpga verilog supports tile modules 2023-07-18 22:35:22 -07:00
Chung Shien Chai b2f5b493c2 Fix the cpp-format 2023-07-16 13:08:40 -07:00
Chung Shien Chai 924622f5e5 Issue 1248 - fix bug bintoi_charvec() 2023-07-15 17:46:43 -07:00
tangxifan 091ac88c7e [lib] code format 2023-07-14 12:16:40 -07:00
tangxifan 3bc959dcec [lib] create tile config lib and start integration to core 2023-07-14 12:13:31 -07:00
tangxifan d0831507c0 [lib] format fabric key writer 2023-07-06 19:21:45 -07:00
tangxifan 85f9899588 [lib] fixed some bugs and now fabric key io is working 2023-07-06 16:30:36 -07:00
tangxifan 74e776f3b0 [lib] syntax errors and now fabric key is under the namespace of openfpga 2023-07-06 11:57:22 -07:00
tangxifan 6c623d60f9 [lib] code format 2023-07-06 11:16:36 -07:00
tangxifan 82a60d64e3 [lib] add api to fabric key 2023-07-05 23:53:16 -07:00
tangxifan ed25cf0dc4 [lib] developing sub key io and APIs 2023-07-05 21:18:33 -07:00
tangxifan c2020d6cef [lib] now use constants in xml io for fabric key 2023-07-04 21:04:21 -07:00
tangxifan 93158bdc62 [lib] adding subkey feature 2023-07-03 15:53:22 -07:00
tangxifan 1b9aeab2a7 [lib] reorganize the source files of libfabrickey 2023-07-03 15:02:23 -07:00
tangxifan 83fa6a421e [core] code format 2023-06-26 10:06:17 -07:00
tangxifan 70f40cd21a [core] fixing bugs in the preconfig module when supporting dut module of fpga_core 2023-06-26 10:03:19 -07:00
tangxifan 987a562e0f [core] fixed the bug when checking mapping status of fpga core ports 2023-06-23 17:21:52 -07:00
tangxifan b30148f8fb [core] apply more sanity checks on top module port 2023-06-23 12:37:46 -07:00
tangxifan d9f271eaed [lib] fixed a bug where constant string is not initialized 2023-06-23 11:18:36 -07:00
tangxifan 8bd9ae02fd [core] io name map now supports dummy port direction 2023-06-23 11:09:33 -07:00
tangxifan 0811409c4f [lib] support dummy port direction in IoNameMap io 2023-06-22 23:20:22 -07:00
tangxifan 7961223eac [core] enabling io naming rules in fabric builder 2023-06-22 22:18:09 -07:00
tangxifan 4d265c3965 [lib] reworked io name map data structure. Passed I/O test 2023-06-22 17:44:07 -07:00
tangxifan a628a1e7b0 [lib] add missing file 2023-06-21 23:02:43 -07:00
tangxifan b8d89d2a5c [lib] code format 2023-06-21 22:51:38 -07:00
tangxifan 227d147dca [lib] add an example file 2023-06-21 22:51:15 -07:00
tangxifan 77b082ab55 [src] debugging 2023-06-21 22:50:37 -07:00
tangxifan f3c07d6138 [lib] finish the io for io naming rules 2023-06-21 21:48:52 -07:00
tangxifan 2ed86d1897 [lib] developing io for io naming rule 2023-06-21 18:08:45 -07:00
tangxifan b42677aa9d [lib] developing the io name mapping data structure 2023-06-21 17:33:40 -07:00
tangxifan c7ade72200 [core] code complete for the core wrapper creator. Start debugging 2023-06-18 19:17:42 -07:00
tangxifan e20ac5f272 [core] fixed a bug which cause configuration protocols other than ccff failed 2023-04-24 22:46:46 +08:00
tangxifan 18b078d1d5 [core] fixed bugs which cause ci failed 2023-04-24 21:20:07 +08:00
tangxifan 667d9df028 [core] developing testbench generator for ccff v2 2023-04-24 11:36:21 +08:00
tangxifan ba90f5020b [core] fixed some bugs which cause netlist generation failed 2023-04-23 16:48:14 +08:00
tangxifan 28b7a12f68 [core] code format 2023-04-23 14:31:35 +08:00
tangxifan bd511ba515 [core] fixed syntax errors 2023-04-23 14:26:08 +08:00
tangxifan 592765af48 [core] code complete for upgrading netlist generator w.r.t. ccff v2 2023-04-23 13:57:37 +08:00
tangxifan 5500b9a289 [core] upgrading netlist generator 2023-04-22 16:27:27 +08:00