tangxifan
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7a5dd1bc02
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[Tools] Patch circuit library for dummy circuit models without any ports
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2021-02-24 10:36:48 -07:00 |
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tangxifan
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0ce9b66c75
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[Arch] Add a dummy adder lut circuit model to support HDL simulation
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2021-02-24 10:09:44 -07:00 |
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tangxifan
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86a602d381
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[Test] Deploy new test to CI
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2021-02-23 19:55:07 -07:00 |
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tangxifan
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a62786986b
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[Test] Turn off verification in adder lut test temporarily
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2021-02-23 19:03:25 -07:00 |
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tangxifan
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df7b436ac7
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[Tool] Patch repacker to support duplicated nets due to adder nets
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2021-02-23 19:01:18 -07:00 |
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tangxifan
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ad25944e59
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[Arch] Patched superLUT architecture example when trying adder8 synthesis script
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2021-02-23 19:00:27 -07:00 |
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tangxifan
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53df7f69e7
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[Test] Bug fix in the test case using lut adder
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2021-02-23 16:59:46 -07:00 |
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tangxifan
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db71cc8a16
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[Test] Add LUT adder test using quicklogic synthesis script
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2021-02-23 16:50:58 -07:00 |
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tangxifan
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154f3b6cfc
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Merge pull request #249 from lnis-uofu/dev
Reorganize QuickLogic's Regression Tests
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2021-02-23 08:35:27 -07:00 |
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tangxifan
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19f6b221b1
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[Test] Rework comments on runtime
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2021-02-22 15:25:57 -07:00 |
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tangxifan
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4803b0ce42
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[Test] Add test case for sdc controller
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2021-02-22 15:02:14 -07:00 |
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tangxifan
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c7a9a4e896
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[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
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2021-02-22 15:01:50 -07:00 |
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tangxifan
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ca135f3325
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[Arch] Add flagship architecture with 8-clock
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2021-02-22 15:01:18 -07:00 |
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tangxifan
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2e2b1cb6e7
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[Test] Use hetergenenous FPGA architecture in quicklogic tests
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2021-02-22 13:41:04 -07:00 |
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tangxifan
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1c09c55e9f
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[Arch] Add hetergenenous 8-clock FPGA architecture
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2021-02-22 13:38:50 -07:00 |
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tangxifan
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b3fed683f9
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[Test] Deploy test to CI
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2021-02-22 12:43:30 -07:00 |
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tangxifan
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bc30f62c5a
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[Test] Add test for sdc controller
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2021-02-22 12:41:53 -07:00 |
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tangxifan
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60dc194d8f
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[Test] Bug fix in the 5clock test case
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2021-02-22 11:46:23 -07:00 |
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tangxifan
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71e0026a50
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[Test] Add new test for 5-clock counter to quicklogic tests
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2021-02-22 11:32:17 -07:00 |
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tangxifan
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2bb588dacf
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[Flow] Add a new script for generating bitstream for multi-clock architectures
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2021-02-22 11:31:24 -07:00 |
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tangxifan
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77896379e2
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[Arch] Add simulation setting for 8-clock architectures
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2021-02-22 11:10:03 -07:00 |
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tangxifan
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16debe49f6
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[Arch] Add more comments on the 4 clock simulation setting file
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2021-02-22 11:04:34 -07:00 |
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tangxifan
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0ac75723af
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[Arch] Add new architecture with 8 clocks
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2021-02-22 11:00:45 -07:00 |
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tangxifan
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b9c2564a7e
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[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
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2021-02-22 10:49:21 -07:00 |
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tangxifan
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bc8aa0ebc6
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[Test] Remove routing test from quicklogic's flow test
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2021-02-22 10:22:47 -07:00 |
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tangxifan
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2dbdc2644f
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[Benchmark] Remove replicate micro benchmarks
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2021-02-22 10:22:19 -07:00 |
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tangxifan
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9b6b2068ee
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[Test] Move MCNC test to benchmark sweep test group
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2021-02-22 10:18:34 -07:00 |
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tangxifan
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c1f4a434e4
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[Doc] Update README for the regression test tasks
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2021-02-22 10:17:02 -07:00 |
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tangxifan
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0384c4c61e
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Merge branch 'master' into dev
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2021-02-22 09:49:03 -07:00 |
ganeshgore
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4315660bf1
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Merge pull request #245 from lnis-uofu/dev
Throw fatal error when the number of configurable region is different between fabric key and architecture definition
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2021-02-22 09:48:23 -07:00 |
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tangxifan
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d6a02a985e
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Merge pull request #248 from lnis-uofu/add_quicklogic_tests
Disabling verilog testbench generation for quicklogic tests
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2021-02-22 09:02:29 -07:00 |
Lalit Sharma
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d842026672
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Disabling verilog testbench generation for quicklogic tests
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2021-02-21 21:58:23 -08:00 |
Lalit Narain Sharma
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be5e0cdea9
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Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
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2021-02-22 09:50:26 +05:30 |
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Lalit Sharma
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576e6753f6
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Removing 2 more tests which are variant of and design
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2021-02-19 09:11:19 -08:00 |
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Lalit Sharma
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d4c5a5655a
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Removing blif file as well as and2 testcase
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2021-02-19 08:55:17 -08:00 |
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Lalit Sharma
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6de0954ca5
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Uncommenting all benchmarks except 2 that requires multiple clocks
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2021-02-19 08:40:26 -08:00 |
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tangxifan
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01b9bf2a02
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[Doc] Update num_region XML for config protocol
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2021-02-18 21:58:30 -07:00 |
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tangxifan
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e6091fb3ff
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[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
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2021-02-18 21:56:30 -07:00 |
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tangxifan
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bcd8256c59
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Merge pull request #243 from lnis-uofu/dev
Bug fix for truth table creation for wired LUT created by repacking
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2021-02-18 20:44:02 -07:00 |
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tangxifan
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e08ac1a41e
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[Test] Deploy synthesizable verilog test to CI
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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e19fc15fec
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[Test] bug fix in test case
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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affc8cbbc4
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[Test] Deploy test to CI
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2021-02-18 19:37:45 -07:00 |
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tangxifan
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2e88b035ed
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[Test] Add wire LUT repacker test case
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2021-02-18 19:37:44 -07:00 |
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tangxifan
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1f097abe99
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[Benchmark] Add micro benchmark for FIR filter
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2021-02-18 19:37:44 -07:00 |
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tangxifan
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a5b8b2a64a
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[Tool] Use dedicated function to identify wire LUT created by repacker
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2021-02-18 19:37:44 -07:00 |
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tangxifan
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aae03482f5
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[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
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ganeshgore
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122218dfd3
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Merge pull request #244 from lnis-uofu/synth_verilog_test_deployment
Deploy synthesizable verilog test to CI
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2021-02-18 10:46:19 -07:00 |
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Lalit Sharma
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69cdc11ea5
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Uncommenting the tests that are running fine
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2021-02-18 04:17:12 -08:00 |
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tangxifan
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a06e7e6c80
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Merge branch 'master' into dev
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2021-02-17 19:46:09 -07:00 |
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tangxifan
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9004e28d47
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Merge branch 'master' into synth_verilog_test_deployment
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2021-02-17 19:45:35 -07:00 |