Merge pull request #249 from lnis-uofu/dev
Reorganize QuickLogic's Regression Tests
This commit is contained in:
tangxifan
GitHub
commit
154f3b6cfc
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@ -1,10 +0,0 @@
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IN0 0.505000 0.204400
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IN1 0.491000 0.206000
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IN2 0.472000 0.204400
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clk 0.500000 2.000000
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OUT1 0.491000 0.206000
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OUT0 0.505000 0.204400
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OUT2 0.472000 0.204400
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n15 0.491000 0.101146
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n18 0.505000 0.103222
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n21 0.472000 0.096477
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@ -1,19 +0,0 @@
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module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);
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input wire IN0,IN1,IN2,clk;
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output reg OUT0, OUT1, OUT2;
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always @(posedge clk)
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begin
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OUT0 <= IN0;
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OUT1 <= IN1;
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OUT2 <= IN2;
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end
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endmodule
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@ -0,0 +1,198 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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- 8 operating clocks
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0"/>
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</circuit_model>
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<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="4"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="16"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" size="1"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="output" prefix="QN" size="1"/>
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<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
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</circuit_model>
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<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
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<port type="input" prefix="outpad" lib_name="A" size="1"/>
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<port type="output" prefix="inpad" lib_name="Y" size="1"/>
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</circuit_model>
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</circuit_library>
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<configuration_protocol>
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<organization type="scan_chain" circuit_model_name="DFF"/>
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</configuration_protocol>
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<connection_block>
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<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
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</connection_block>
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<switch_block>
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<switch name="0" circuit_model_name="mux_tree_tapbuf"/>
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</switch_block>
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<routing_segment>
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<tile_annotations>
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<global_port name="clk" is_clock="true" default_val="0">
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<!-- MUST explicitly define the number of clock bits
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being consistent with physical tile port definition
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-->
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<tile name="clb" port="clk[0:7]" x="-1" y="-1"/>
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</global_port>
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</tile_annotations>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
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<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb">
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<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
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<interconnect name="crossbar" circuit_model_name="mux_tree"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
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<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
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<!-- End physical pb_type binding in complex block IO -->
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</pb_type_annotations>
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</openfpga_architecture>
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@ -0,0 +1,448 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
|
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- General purpose logic block
|
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- K = 6, N = 10, I = 40
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- Single mode
|
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
|
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<design vdd="2.5" pn_ratio="3"/>
|
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
|
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</device_model>
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</device_library>
|
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<variation_library>
|
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
|
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
|
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</technology_library>
|
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<circuit_library>
|
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
|
||||
<design_technology type="cmos" topology="inverter" size="1"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
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<port type="output" prefix="out" size="1"/>
|
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<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
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</delay_matrix>
|
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<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
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</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
|
||||
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<device_technology device_model_name="logic"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="input" prefix="sel" size="1"/>
|
||||
<port type="input" prefix="selb" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="false"/>
|
||||
<output_buffer exist="false"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||
<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="false" default_val="0" />
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
|
||||
<lut_input_buffer exist="true" circuit_model_name="buf4"/>
|
||||
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
|
||||
<pass_gate_logic circuit_model_name="TGATE"/>
|
||||
<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
|
||||
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="64"/>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="QN" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
|
||||
<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
<port type="input" prefix="outpad" lib_name="A" size="1"/>
|
||||
<port type="output" prefix="inpad" lib_name="Y" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="1"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="1"/>
|
||||
<port type="input" prefix="cin" lib_name="CI" size="1"/>
|
||||
<port type="output" prefix="sumout" lib_name="SUM" size="1"/>
|
||||
<port type="output" prefix="cout" lib_name="CO" size="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="mult_36x36" prefix="mult_36x36" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mult_36x36.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mult_36x36.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="a" lib_name="A" size="36"/>
|
||||
<port type="input" prefix="b" lib_name="B" size="36"/>
|
||||
<port type="output" prefix="out" size="72"/>
|
||||
<!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="hard_logic" name="frac_mem_32k" prefix="frac_mem_32k" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/frac_mem_32k.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<output_buffer exist="true" circuit_model_name="INVTX1"/>
|
||||
<port type="input" prefix="addr1" lib_name="addr_a" size="15"/>
|
||||
<port type="input" prefix="addr2" lib_name="addr_b" size="15"/>
|
||||
<port type="input" prefix="data1" lib_name="data_a" size="32"/>
|
||||
<port type="input" prefix="data2" lib_name="data_b" size="32"/>
|
||||
<port type="input" prefix="we1" lib_name="we_a" size="1"/>
|
||||
<port type="input" prefix="we2" lib_name="we_b" size="1"/>
|
||||
<port type="output" prefix="out1" lib_name="q_a" size="32"/>
|
||||
<port type="output" prefix="out2" lib_name="q_b" size="32"/>
|
||||
<port type="clock" prefix="clk" size="1" is_global="false" default_val="0"/>
|
||||
<!-- As a fracturable memory, it requires 4 configuration bits to operate in 13 different modes -->
|
||||
<port type="sram" prefix="mode" size="4" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
|
||||
</circuit_model>
|
||||
</circuit_library>
|
||||
<configuration_protocol>
|
||||
<organization type="scan_chain" circuit_model_name="DFFR"/>
|
||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<direct_connection>
|
||||
<direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
|
||||
</direct_connection>
|
||||
<tile_annotations>
|
||||
<global_port name="clk" is_clock="true" default_val="0">
|
||||
<!-- MUST explicitly define the number of clock bits
|
||||
being consistent with physical tile port definition
|
||||
-->
|
||||
<tile name="clb" port="clk[0:7]" x="-1" y="-1"/>
|
||||
<tile name="memory" port="clk[0:7]" x="-1" y="-1"/>
|
||||
</global_port>
|
||||
</tile_annotations>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle" physical_mode_name="physical"/>
|
||||
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
|
||||
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
|
||||
<pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
|
||||
<!-- Binding operating pb_type to physical pb_type -->
|
||||
<!-- Binding operating pb_types in mode 'n2_lut5' -->
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
|
||||
<!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:4]"/>
|
||||
<port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'arithmetic' -->
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
|
||||
<!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:3]"/>
|
||||
<port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
|
||||
<pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
|
||||
<!-- Binding operating pb_types in mode 'ble6' -->
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
|
||||
<!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
|
||||
<port name="in" physical_mode_port="in[0:5]"/>
|
||||
<port name="out" physical_mode_port="lut6_out"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
|
||||
<!-- End physical pb_type binding in complex block clb -->
|
||||
|
||||
<!-- physical pb_type binding in complex block dsp -->
|
||||
<pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
|
||||
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
|
||||
<pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/>
|
||||
<!-- Bind the 9x9 multiplier to the physical 36x36 multiplier
|
||||
There are four 9x9 multipliers, each of which occupies part
|
||||
of the input/output of the 36x36 multiplier
|
||||
-->
|
||||
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
|
||||
<port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
|
||||
<port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 18x18 multiplier to the physical 36x36 multiplier
|
||||
There are two 18x18 multipliers, each of which occupies part
|
||||
of the input/output of the 36x36 multiplier
|
||||
-->
|
||||
<pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult_18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
|
||||
<port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
|
||||
<port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
|
||||
</pb_type>
|
||||
<!-- END physical pb_type binding in complex block dsp -->
|
||||
|
||||
<!-- physical pb_type binding in complex block memory -->
|
||||
<pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/>
|
||||
<pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/>
|
||||
<!-- Bind the 512x64 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
|
||||
<port name="addr" physical_mode_port="addr1[0:8]"/>
|
||||
<port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="0 -32"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="0 -32"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 1024x32 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
|
||||
<port name="addr" physical_mode_port="addr1[0:9]"/>
|
||||
<port name="data" physical_mode_port="data1"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 2048x16 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
|
||||
<port name="addr" physical_mode_port="addr1[0:10]"/>
|
||||
<port name="data" physical_mode_port="data1[0:15]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:15]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 4096x8 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
|
||||
<port name="addr" physical_mode_port="addr1[0:11]"/>
|
||||
<port name="data" physical_mode_port="data1[0:7]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:7]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 8192x4 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
|
||||
<port name="addr" physical_mode_port="addr1[0:12]"/>
|
||||
<port name="data" physical_mode_port="data1[0:3]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:3]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 16384x2 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
|
||||
<port name="addr" physical_mode_port="addr1[0:13]"/>
|
||||
<port name="data" physical_mode_port="data1[0:1]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:1]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 32768x1 single port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
|
||||
<port name="addr" physical_mode_port="addr1[0:14]"/>
|
||||
<port name="data" physical_mode_port="data1[0:0]"/>
|
||||
<port name="we" physical_mode_port="we1"/>
|
||||
<port name="out" physical_mode_port="out1[0:0]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 1024x32 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0111">
|
||||
<port name="addr1" physical_mode_port="addr1[0:9]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:9]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:31]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:31]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:31]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:31]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 2048x16 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
|
||||
<port name="addr1" physical_mode_port="addr1[0:10]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:10]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:15]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:15]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:15]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:15]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 4096x8 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
|
||||
<port name="addr1" physical_mode_port="addr1[0:11]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:11]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:7]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:7]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:7]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:7]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 8192x4 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
|
||||
<port name="addr1" physical_mode_port="addr1[0:12]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:12]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:3]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:3]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:3]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:3]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 16384x2 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
|
||||
<port name="addr1" physical_mode_port="addr1[0:13]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:13]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:1]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:1]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:1]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:1]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- Bind the 32768x1 dual port RAM to the physical implementation -->
|
||||
<pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
|
||||
<port name="addr1" physical_mode_port="addr1[0:14]"/>
|
||||
<port name="addr2" physical_mode_port="addr2[0:14]"/>
|
||||
<port name="data1" physical_mode_port="data1[0:0]"/>
|
||||
<port name="data2" physical_mode_port="data2[0:0]"/>
|
||||
<port name="we1" physical_mode_port="we1"/>
|
||||
<port name="we2" physical_mode_port="we2"/>
|
||||
<port name="out1" physical_mode_port="out1[0:0]"/>
|
||||
<port name="out2" physical_mode_port="out2[0:0]"/>
|
||||
<port name="clk" physical_mode_port="clk"/>
|
||||
</pb_type>
|
||||
<!-- END physical pb_type binding in complex block memory -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
# Run VPR for the 'and' design
|
||||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
# Note: no need to assign activity file when you used a fixed number
|
||||
# of clock cycles in simulation settings
|
||||
# Also, ACE2 does not support multiple clocks
|
||||
# Therefore, activity file is not recommended for multi-clock fabric/implementations
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
# - Enabled frame view creation to save runtime and memory
|
||||
# Note that this is turned on when bitstream generation
|
||||
# is the ONLY purpose of the flow!!!
|
||||
build_fabric --compress_routing --frame_view #--verbose
|
||||
|
||||
# Write the fabric hierarchy of module graph to a file
|
||||
# This is used by hierarchical PnR flows
|
||||
write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINTS_FILE} #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
|
||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
# Run VPR for the 'and' design
|
||||
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
|
||||
# This is due to the Fc_in of clock port is set to 0 for global wiring
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
# Note: no need to assign activity file when you used a fixed number
|
||||
# of clock cycles in simulation settings
|
||||
# Also, ACE2 does not support multiple clocks
|
||||
# Therefore, activity file is not recommended for multi-clock fabric/implementations
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
# - Enabled frame view creation to save runtime and memory
|
||||
# Note that this is turned on when bitstream generation
|
||||
# is the ONLY purpose of the flow!!!
|
||||
build_fabric --compress_routing --frame_view #--verbose
|
||||
|
||||
# Write the fabric hierarchy of module graph to a file
|
||||
# This is used by hierarchical PnR flows
|
||||
write_fabric_hierarchy --file ./fabric_hierarchy.txt
|
||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack --design_constraints ${OPENFPGA_REPACK_DESIGN_CONSTRAINTS_FILE} #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
|
||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.xml --format xml
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
@ -12,6 +12,10 @@
|
|||
Note that
|
||||
- clock name must be unique as it is used in testbench genertion
|
||||
- the clock port must match clock port definition in OpenFPGA architecture XML!!!
|
||||
|
||||
Note: This clock setting is also applicable to architectures with 4+ clocks
|
||||
In that case, the first 4-bit of the clock port will be driven by different clock frequencies
|
||||
while the rest bits of the clock port will be driven by the default clock frequency
|
||||
-->
|
||||
<operating frequency="50e6" num_cycles="20" slack="0.2">
|
||||
<clock name="clk_10MHz" port="clk[0:0]" frequency="10e6"/>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,59 @@
|
|||
<!-- Simulation Setting for OpenFPGA framework
|
||||
This file will use automatic inference for any settings
|
||||
including:
|
||||
- auto select the number of simulation cycles
|
||||
- auto select the simulation clock frequency from VPR results
|
||||
-->
|
||||
<openfpga_simulation_setting>
|
||||
<clock_setting>
|
||||
<!-- The frequency defined in the operating line will be
|
||||
the default operating clock frequency for all the clocks
|
||||
define specific frequency using <clock> line will overwrite the default value
|
||||
Note that
|
||||
- clock name must be unique as it is used in testbench genertion
|
||||
- the clock port must match clock port definition in OpenFPGA architecture XML!!!
|
||||
|
||||
Note: This clock setting is also applicable to architectures with 8+ clocks
|
||||
In that case, the first 8-bit of the clock port will be driven by different clock frequencies
|
||||
while the rest bits of the clock port will be driven by the default clock frequency
|
||||
-->
|
||||
<operating frequency="50e6" num_cycles="20" slack="0.2">
|
||||
<clock name="clk_10MHz" port="clk[0:0]" frequency="10e6"/>
|
||||
<clock name="clk_20MHz" port="clk[1:1]" frequency="20e6"/>
|
||||
<clock name="clk_30MHz" port="clk[2:2]" frequency="30e6"/>
|
||||
<clock name="clk_40MHz" port="clk[3:3]" frequency="40e6"/>
|
||||
<clock name="clk_50MHz" port="clk[4:4]" frequency="50e6"/>
|
||||
<clock name="clk_60MHz" port="clk[5:5]" frequency="60e6"/>
|
||||
<clock name="clk_70MHz" port="clk[6:6]" frequency="70e6"/>
|
||||
<clock name="clk_80MHz" port="clk[7:7]" frequency="80e6"/>
|
||||
</operating>
|
||||
<programming frequency="100e6"/>
|
||||
</clock_setting>
|
||||
<simulator_option>
|
||||
<operating_condition temperature="25"/>
|
||||
<output_log verbose="false" captab="false"/>
|
||||
<accuracy type="abs" value="1e-13"/>
|
||||
<runtime fast_simulation="true"/>
|
||||
</simulator_option>
|
||||
<monte_carlo num_simulation_points="2"/>
|
||||
<measurement_setting>
|
||||
<slew>
|
||||
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
|
||||
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
|
||||
</slew>
|
||||
<delay>
|
||||
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||||
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
|
||||
</delay>
|
||||
</measurement_setting>
|
||||
<stimulus>
|
||||
<clock>
|
||||
<rise slew_type="abs" slew_time="20e-12" />
|
||||
<fall slew_type="abs" slew_time="20e-12" />
|
||||
</clock>
|
||||
<input>
|
||||
<rise slew_type="abs" slew_time="25e-12" />
|
||||
<fall slew_type="abs" slew_time="25e-12" />
|
||||
</input>
|
||||
</stimulus>
|
||||
</openfpga_simulation_setting>
|
||||
|
|
@ -10,3 +10,7 @@ echo -e "QuickLogic regression tests";
|
|||
|
||||
echo -e "Testing yosys flow using custom ys script for running quicklogic device";
|
||||
run-task quicklogic_tests/flow_test --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing yosys flow using custom ys script for running multi-clock quicklogic device";
|
||||
run-task quicklogic_tests/counter_5clock_test --debug --show_thread_logs
|
||||
run-task quicklogic_tests/sdc_controller_test --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -19,5 +19,8 @@ The principle is that each OpenFPGA tool should have a set of regression tests.
|
|||
|
||||
- FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.
|
||||
|
||||
- Quicklogic regression test is to ensure working flows for QuickLogic's devices and variants
|
||||
|
||||
- Benchmark sweep regression test should focus on testing mainly the bitstream generation for a wide range of benchmark suites
|
||||
|
||||
Please keep this README up-to-date on the OpenFPGA tools
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
<pin_constraints>
|
||||
<!-- For a given .blif file, we want to assign
|
||||
- the clk0 signal to the clk[0] port of the FPGA fabric
|
||||
- the clk1 signal to the clk[1] port of the FPGA fabric
|
||||
-->
|
||||
<set_io pin="clk[0]" net="clk1"/>
|
||||
<set_io pin="clk[1]" net="clk2"/>
|
||||
<set_io pin="clk[2]" net="clk3"/>
|
||||
<set_io pin="clk[3]" net="clk4"/>
|
||||
<set_io pin="clk[4]" net="clk5"/>
|
||||
</pin_constraints>
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<repack_design_constraints>
|
||||
<!-- For a given .blif file, we want to assign
|
||||
- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
|
||||
- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
|
||||
and ensure no signals could be mapped to
|
||||
- the clk[2] port of all the clb tiles available in the FPGA fabric
|
||||
- the clk[3] port of all the clb tiles available in the FPGA fabric
|
||||
-->
|
||||
<pin_constraint pb_type="clb" pin="clk[0]" net="clk1"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[1]" net="clk2"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[2]" net="clk3"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[3]" net="clk4"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[4]" net="clk5"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[5]" net="OPEN"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[6]" net="OPEN"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[7]" net="OPEN"/>
|
||||
</repack_design_constraints>
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = false
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 1*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
|
||||
openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
|
||||
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = counter120bitx5
|
||||
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
|
|
@ -28,7 +28,6 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rt
|
|||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
|
||||
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
|
||||
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v
|
||||
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.v
|
||||
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
|
||||
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
|
||||
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
|
||||
|
|
@ -56,8 +55,6 @@ bench2_top = bin2bcd
|
|||
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
|
||||
bench3_top = counter
|
||||
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
|
||||
bench4_top = routing_test
|
||||
bench4_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
|
||||
bench5_top = rs_decoder_top
|
||||
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
|
||||
bench6_top = top_module
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
<pin_constraints>
|
||||
<!-- For a given .blif file, we want to assign
|
||||
- the clk0 signal to the clk[0] port of the FPGA fabric
|
||||
- the clk1 signal to the clk[1] port of the FPGA fabric
|
||||
-->
|
||||
<set_io pin="clk[0]" net="wb_clk_i"/>
|
||||
<set_io pin="clk[1]" net="sd_clk_i_pad"/>
|
||||
<set_io pin="clk[2]" net="sd_clk_o_pad"/>
|
||||
</pin_constraints>
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
<repack_design_constraints>
|
||||
<!-- For a given .blif file, we want to assign
|
||||
- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
|
||||
- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
|
||||
and ensure no signals could be mapped to
|
||||
- the clk[2] port of all the clb tiles available in the FPGA fabric
|
||||
- the clk[3] port of all the clb tiles available in the FPGA fabric
|
||||
-->
|
||||
<pin_constraint pb_type="clb" pin="clk[0]" net="wb_clk_i"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[1]" net="sd_clk_i_pad"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[2]" net="sd_clk_o_pad"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[4]" net="OPEN"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[5]" net="OPEN"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[6]" net="OPEN"/>
|
||||
<pin_constraint pb_type="clb" pin="clk[7]" net="OPEN"/>
|
||||
</repack_design_constraints>
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = false
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
# Runtime is around 3 minutes
|
||||
# But it can be efficiently reduced by improving synthesis script
|
||||
# (See detailed comments in Synthesis parameter section)
|
||||
timeout_each_job = 5*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
|
||||
openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/repack_pin_constraints.xml
|
||||
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/pin_constraints.xml
|
||||
openfpga_vpr_route_chan_width=200
|
||||
openfpga_vpr_device_layout=32x32
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_GlobalTile8Clk_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = sdc_controller
|
||||
# Use standard script for now because QL synthesis recipe generates $DFF_PP model
|
||||
# Also current synthesis recipe does not support FIFO, BRAM and multiplier
|
||||
# which causes runtime to be long
|
||||
#bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
<!--
|
||||
Architecture with no fracturable LUTs
|
||||
|
||||
- 40 nm technology
|
||||
- General purpose logic block:
|
||||
K = 4, N = 4
|
||||
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
||||
- 8 operating clocks which can be selected for each logic element
|
||||
|
||||
Details on Modelling:
|
||||
|
||||
Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. This architecture has no fracturable LUTs nor any heterogeneous blocks.
|
||||
|
||||
|
||||
Authors: Jason Luu, Jeff Goeders, Vaughn Betz
|
||||
-->
|
||||
<architecture>
|
||||
<!--
|
||||
ODIN II specific config begins
|
||||
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||
".model [type_of_block]") that this architecture supports.
|
||||
|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<tile name="io" capacity="8" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad</loc>
|
||||
<loc side="top">io.outpad io.inpad</loc>
|
||||
<loc side="right">io.outpad io.inpad</loc>
|
||||
<loc side="bottom">io.outpad io.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<tile name="clb" area="53894">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="10" equivalent="full"/>
|
||||
<output name="O" num_pins="4" equivalent="none"/>
|
||||
<clock name="clk" num_pins="8"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<pinlocations pattern="spread"/>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="2x2" width="4" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<complexblocklist>
|
||||
<!-- Define I/O pads begin -->
|
||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||
-->
|
||||
<!-- Place I/Os on the sides of the FPGA -->
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define general purpose logic block (CLB) begin -->
|
||||
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||
block. Note that the crossbar / local interconnect is considered part of the logic block
|
||||
area in this analysis. That is a lower proportion of of routing area than most academics
|
||||
assume, but note that the total routing area really includes the crossbar, which would push
|
||||
routing area up significantly, we estimate into the ~70% range.
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="10" equivalent="full"/>
|
||||
<output name="O" num_pins="4" equivalent="none"/>
|
||||
<clock name="clk" num_pins="8"/>
|
||||
<!-- Describe basic logic element.
|
||||
Each basic logic element has a 4-LUT that can be optionally registered
|
||||
-->
|
||||
<pb_type name="fle" num_pb="4">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- 4-LUT mode definition begin -->
|
||||
<mode name="n1_lut4">
|
||||
<!-- Define 4-LUT mode -->
|
||||
<pb_type name="ble4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 6-LUT mode definition end -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||
The delays below come from Stratix IV. the delay through a connection block
|
||||
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||
delay within the crossbar is 95 ps.
|
||||
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
naive specification).
|
||||
-->
|
||||
<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
|
||||
</interconnect>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- Place this general purpose logic block in any unspecified column -->
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
File diff suppressed because it is too large
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Reference in New Issue