tangxifan
|
a7d900088b
|
now generating simulation ini file will try to create directory first
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2020-04-15 20:53:37 -06:00 |
|
tangxifan
|
72e8824a87
|
bug fixed on removing undriven pins (direct connection between clbs) from cb
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2020-04-15 20:41:15 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
|
tangxifan
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032ebc29e6
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-04-15 12:53:20 -06:00 |
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tangxifan
|
1e742a3676
|
add test case on auto-check test benches
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2020-04-15 12:52:52 -06:00 |
ganeshgore
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689c4a3e19
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BugFix: The filename in the previous commit
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2020-04-15 12:44:22 -06:00 |
|
tangxifan
|
46fe1e84ce
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Merge branch 'dev' into ganesh_dev
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2020-04-15 12:27:51 -06:00 |
|
ganeshgore
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7f37bf1441
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Added formal verification support to fpga_flow script
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2020-04-15 12:24:51 -06:00 |
|
tangxifan
|
56e0d2a918
|
critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
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2020-04-13 12:58:44 -06:00 |
|
tangxifan
|
07a384e440
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now use openfpga tokenizer to trim command line string in openfpga shell
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2020-04-13 11:08:31 -06:00 |
|
tangxifan
|
7ba3e27371
|
add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
|
tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
|
tangxifan
|
59ea0a6ad5
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add implicit verilog test case to Travis CI
|
2020-04-12 20:00:20 -06:00 |
|
tangxifan
|
23aef96d3a
|
add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
|
tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
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2020-04-12 19:07:53 -06:00 |
|
tangxifan
|
a614e5aad9
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add long adder chain to Travis CI
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2020-04-12 15:43:19 -06:00 |
|
tangxifan
|
f71a85a1d4
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add test cases on different routing multiplexer circuit designs to Travis CI
|
2020-04-12 15:39:45 -06:00 |
|
tangxifan
|
214d98fbcd
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add register chain and scan chain to Travis CI
|
2020-04-12 15:28:22 -06:00 |
|
tangxifan
|
148cc74d6a
|
add io test cases to Travis CI
|
2020-04-12 15:01:47 -06:00 |
|
tangxifan
|
da5af8f0e0
|
try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
|
tangxifan
|
28cb412359
|
add test case of wide BRAM 16k to Travis CI
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2020-04-12 14:37:08 -06:00 |
|
tangxifan
|
5d665aa04b
|
reshape bram test case
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2020-04-12 14:32:09 -06:00 |
|
tangxifan
|
600a48edc7
|
add test case of BRAM to Travis CI
|
2020-04-12 14:27:05 -06:00 |
|
tangxifan
|
2444752de8
|
add untileable test case to Travis CI
|
2020-04-12 14:08:24 -06:00 |
|
tangxifan
|
cc7adae91e
|
deploy openfpga shell in Travis CI
|
2020-04-12 12:57:13 -06:00 |
|
tangxifan
|
d806ad3148
|
add testcases using openfpga_shell in openfpga_flow
|
2020-04-12 12:54:21 -06:00 |
|
tangxifan
|
68fd296e14
|
add more test vpr architecture to regression tests
|
2020-04-12 12:49:16 -06:00 |
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ganeshgore
|
80bdb41df6
|
Updated task file to run formal verification
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2020-04-11 18:30:21 -06:00 |
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ganeshgore
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e6de0cdce0
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-11 18:05:31 -06:00 |
|
tangxifan
|
49ddbf98c3
|
add more testing architecture to openfpga_flow
|
2020-04-11 18:01:09 -06:00 |
|
tangxifan
|
130b78ca74
|
update arch in openfpga_flow
|
2020-04-11 18:00:37 -06:00 |
|
tangxifan
|
c67a480d6f
|
Merge branch 'ganesh_dev' into dev
|
2020-04-11 16:48:56 -06:00 |
|
ganeshgore
|
f6b3c5854a
|
Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
|
2020-04-11 16:45:22 -06:00 |
|
Xifan Tang
|
b4542ea34b
|
minor fix on doc about the global and general purpose port
|
2020-04-09 17:10:04 -06:00 |
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tangxifan
|
6db4a1290d
|
Merge pull request #51 from LNIS-Projects/ganesh_dev
Ganesh dev
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2020-04-08 21:59:28 -06:00 |
|
ganeshgore
|
8ea272dc2c
|
Patched the OpenFPGA shell execution bug
|
2020-04-08 21:28:14 -06:00 |
|
ganeshgore
|
8267d78b01
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-08 18:40:39 -06:00 |
|
Xifan Tang
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d99776b260
|
update documentation on the global I/O ports
|
2020-04-08 18:18:53 -06:00 |
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tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
b9dab2baaf
|
add exit codes to command execution in shell context
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2020-04-08 16:18:05 -06:00 |
|
Xifan Tang
|
b9ade3fcb6
|
documentation update to introduce new features in script mode of OpenFPGA shell
|
2020-04-08 14:13:28 -06:00 |
|
tangxifan
|
caef468c95
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-04-08 12:56:06 -06:00 |
|
tangxifan
|
1fb37f4c71
|
improve directory creator to support same functionality as 'mkdir -p'
|
2020-04-08 12:55:09 -06:00 |
|
ganeshgore
|
583a4d8767
|
Fixed bug in openfpga_flow script
|
2020-04-08 12:04:08 -06:00 |
|
ganeshgore
|
75edf5912f
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-08 11:39:25 -06:00 |
|
tangxifan
|
f9e055c551
|
Merge branch 'ganesh_dev' into dev
|
2020-04-08 10:56:16 -06:00 |
|
tangxifan
|
e31dc1f2f2
|
openfpga shell now support continued line charactor '\'
|
2020-04-07 21:27:51 -06:00 |
|
tangxifan
|
33315f0521
|
now openfpga shell allow empty space at beginning and end of each line in script mode
|
2020-04-07 20:46:45 -06:00 |
|
tangxifan
|
0b1c8ac139
|
bug fixed in identifying the physical interconnect for pb_graph nodes
|
2020-04-07 19:46:42 -06:00 |
|
tangxifan
|
62276f9e28
|
minor code format
|
2020-04-07 18:43:11 -06:00 |