tangxifan
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f93d46a870
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[OpenFPGA Tool] Add multiple configuration chain support in top module builder
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2020-09-28 19:03:19 -06:00 |
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tangxifan
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552dddffd0
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[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |
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tangxifan
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052b8b71c7
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[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
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2020-09-27 20:54:58 -06:00 |
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tangxifan
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6bea712db0
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[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
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tangxifan
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9adeb550dc
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[OpenFPGA Tool] Bug fix in fabric builder
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2020-09-23 18:28:00 -06:00 |
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tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
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66e5e141a1
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improve fabric key loader to reduce runtime
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2020-07-07 10:19:34 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
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adee87569d
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enable fast bitstream building by creating a frame view of fabric
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2020-07-02 16:25:36 -06:00 |
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tangxifan
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81ecfa3197
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add comments to clarify how to select CB ports when connecting to SBs at the top level
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2020-07-01 14:44:40 -06:00 |
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tangxifan
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0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
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1015880d0e
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use easy-to-access net look up in switch block module builder
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2020-06-30 18:15:41 -06:00 |
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tangxifan
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05187f8aa4
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use typedef to short the module pin information
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2020-06-30 18:07:22 -06:00 |
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tangxifan
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2e7684b746
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adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
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2ef083c49d
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adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
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f023652ac4
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keep optimizing memory footprint of module manager by using net terminal storage
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2020-06-30 14:18:05 -06:00 |
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tangxifan
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f49cabeeda
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optimize memory efficiency for module net id storage
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2020-06-30 11:33:06 -06:00 |
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tangxifan
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23bcad0678
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use more robust net builder in inter tile connections
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2020-06-30 10:49:17 -06:00 |
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tangxifan
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025d4a3599
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use efficient net builder in top module connection builder
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2020-06-29 23:28:26 -06:00 |
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tangxifan
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e7d5736269
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add profile time to top module builder for better spot on runtime/memory overhead sources
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2020-06-29 23:17:03 -06:00 |
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tangxifan
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57e6c84252
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add reserve net sources and sinks to module manager
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2020-06-29 22:49:11 -06:00 |
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tangxifan
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66746f69da
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optimizing memory efficiency by reserving nets in module manager
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2020-06-29 21:27:43 -06:00 |
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tangxifan
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9d32a5b81f
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add alias name support for fabric key
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2020-06-27 14:59:53 -06:00 |
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tangxifan
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a5055e9d26
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add support about loading external fabric key
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2020-06-12 13:03:11 -06:00 |
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tangxifan
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9dbf536306
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add shuffled configurable children support for top module
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2020-06-12 11:16:53 -06:00 |
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tangxifan
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cf9c3b0f44
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add write fabric to test cases
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2020-06-12 10:50:23 -06:00 |
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tangxifan
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3499b4d3e7
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add fabric key writer for top-level module
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2020-06-12 10:41:34 -06:00 |
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tangxifan
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8a4ec85c39
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add configurable children-related methods to module manager
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2020-06-11 21:44:25 -06:00 |
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tangxifan
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3c10af7f2b
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bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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8ec8ac4118
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bug fixed in flatten memory organization. Passed verification
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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b9aac3cbdf
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updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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d2d443a988
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start developing memory bank and standalone configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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bf9f62f0f7
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keep bug fixing for frame-based configuration protocol.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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c696e3d20f
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refine frame-based memory addition to compact the area
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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10e1a4b2fe
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format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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5a8c05378e
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add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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6aff33dd35
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add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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56e0d2a918
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critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
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2020-04-13 12:58:44 -06:00 |