tangxifan
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2306b17d9f
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added pin duplication support to grid module builder
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2019-12-25 22:24:44 -07:00 |
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tangxifan
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868c573e59
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remove unused codes and parameters
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2019-12-24 20:43:29 -07:00 |
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tangxifan
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5445047863
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renamed grid and routing track naming, which are now independent from coordinates
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2019-12-24 20:17:11 -07:00 |
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tangxifan
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0eebdaf942
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add grid port naming function for modules
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2019-12-24 15:07:03 -07:00 |
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tangxifan
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43e78585ba
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add routing track naming function for unique modules
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2019-12-24 14:55:17 -07:00 |
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tangxifan
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0dd72999d5
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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tangxifan
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0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
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876733f052
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now we use module manager to generate analysis SDC, being independent from VPR structures
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2019-11-10 21:15:34 -07:00 |
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tangxifan
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a849522be9
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refactored CB SDC analysis generation
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2019-11-10 20:15:16 -07:00 |
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tangxifan
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8e8e59b0ca
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give specific name to mux so that we can bind it to SDC generator
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2019-11-10 19:42:30 -07:00 |
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tangxifan
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1f368abfbe
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refactoring analysis SDC generation
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2019-11-10 15:40:54 -07:00 |
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tangxifan
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bcd8237263
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refactored grid PnR SDC generator
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2019-11-09 20:57:54 -07:00 |
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tangxifan
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4b5ecc516b
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refactored SDC SB constrain generation
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2019-11-09 10:52:15 -07:00 |
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tangxifan
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be574b0d45
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refactored disable routing mux outputs
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2019-11-08 19:05:05 -07:00 |
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tangxifan
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e273c00c9d
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add refactored disable timing for memory cells
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2019-11-08 17:38:07 -07:00 |
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tangxifan
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33b3705ced
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refactoring disable outputs sdc generation
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2019-11-08 11:15:35 -07:00 |
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tangxifan
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35e718b32d
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rename backend sdc generator to be backend assistant
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2019-11-08 10:20:12 -07:00 |
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tangxifan
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14e7744fee
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start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator
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2019-11-07 22:20:48 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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aac4ccb279
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fixing bug for heterogeneous FPGAs
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2019-11-06 11:19:17 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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5d507ae8ee
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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tangxifan
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3669a47d3b
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
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55eea6c4d5
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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tangxifan
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2b06cfc3cf
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added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
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tangxifan
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f116351831
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add instance name for each pb graph node
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2019-10-26 17:25:45 -06:00 |
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tangxifan
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7649d9228e
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fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
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tangxifan
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0a9c89be0b
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add bitstream writers and start debugging
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2019-10-26 12:41:23 -06:00 |
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tangxifan
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3310bac65b
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refactored grid bitstream generation
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2019-10-25 21:49:47 -06:00 |
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tangxifan
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4b7a9dfa63
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add instance name correlation between module and bitstream generation
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2019-10-25 13:06:48 -06:00 |
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tangxifan
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0b687669c8
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affliate configuration bitstream to sb blocks
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2019-10-25 10:42:12 -06:00 |
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tangxifan
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838173f3c4
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start refactoring bitstream generator
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2019-10-24 21:01:11 -06:00 |
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tangxifan
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13c62fdcf8
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add more methods to bitstream manager (renamed from bitstream context)
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2019-10-24 15:43:29 -06:00 |
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tangxifan
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f26dbfe080
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add instance name for top-level modules to ease readability
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2019-10-23 20:24:52 -06:00 |
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tangxifan
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2787a07f0d
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start refactoring bitstream generation
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2019-10-23 17:34:21 -06:00 |
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tangxifan
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a18f1305cd
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add configurable child list to module manager
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2019-10-23 15:44:13 -06:00 |
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tangxifan
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12162a02bc
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critical bug fixing for compact routing hierarchy and top module generation
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2019-10-23 14:20:04 -06:00 |
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tangxifan
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fb2f003d5b
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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tangxifan
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dafab3907e
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refactored routing module generation and verilog writing
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2019-10-23 11:46:55 -06:00 |
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tangxifan
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9cf8683acd
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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tangxifan
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f002f7e30f
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add const 0 and 1 module Verilog generation
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2019-10-21 14:17:09 -06:00 |
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tangxifan
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b2f57ecf81
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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tangxifan
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520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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tangxifan
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04f0fbebf7
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plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
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tangxifan
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7c1bce4b59
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add module builders for essential gates
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2019-10-18 20:41:05 -06:00 |
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tangxifan
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3b82d62d03
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start developing module graph builders
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2019-10-18 20:02:02 -06:00 |
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tangxifan
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db38f21412
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
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tangxifan
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8c1158fc5c
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |