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OpenFPGA
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4,455 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

257 Commits

Author SHA1 Message Date
tangxifan 4e2df9d69c [Lib] Bug fix in unintialized memory in fabric key 2021-10-10 17:59:11 -07:00
tangxifan 92eebd9abb [Lib] Upgrade fabric key writer to support the BL/WL shift register banks 2021-10-07 17:05:35 -07:00
tangxifan eddafb42c8 [Lib] Upgrade parser for fabric key to support shift register banks 2021-10-07 15:38:42 -07:00
tangxifan a15798a4e1 [Lib] Upgrade fabric key data structure to support shift register bank definitions 2021-10-07 14:42:21 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 3d062872de [Lib] Upgrade openfpga arch parser to error out for unsupported configuration protocol settings 2021-10-05 14:08:01 -07:00
tangxifan 977d81679d [Engine] Upgrade check codes for WL CCFF 2021-10-01 17:23:10 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan 4926c323e7 [Engine] Bug fix due to the optional syntax ``num_bank`` were required in XML 2021-09-29 16:32:29 -07:00
tangxifan 834bdd2b07 [Engine] Updating fabric generator to support BL/WL shift registers. Still WIP 2021-09-28 17:29:03 -07:00
tangxifan afd03d7eb7 [Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers 2021-09-28 15:56:07 -07:00
tangxifan 0a2979d616 [Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols 2021-09-28 14:20:35 -07:00
tangxifan 8b72447dad [FPA-Bistream] Updating fabric bitstream writer to organize bitstream for flatten BL/WLs 2021-09-24 18:07:07 -07:00
tangxifan a49e3fe57a [FPGA-bitstream] Upgraded bitstream generator to support flatten BL/WLs for QL memory bank 2021-09-24 16:30:18 -07:00
tangxifan 5f7617b682 [Engine] Clear up compiler warnings in circuit library 2021-09-24 15:18:50 -07:00
tangxifan f735c10b84 [Engine] Clear up compiler warnings 2021-09-24 15:18:31 -07:00
tangxifan be4c850d2d [Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs 2021-09-24 12:03:35 -07:00
tangxifan 6645b70ae3 [Engine] Upgrade parser to support BL/WL protocols 2021-09-23 14:25:25 -07:00
tangxifan d4e3445153 [Engine] update internal data structure for new syntax in configuration protocol 2021-09-22 17:32:45 -07:00
tangxifan e09ab2298e [Engine] Bug fix in fabric key parser on identifying invalid coordinate 2021-09-21 16:45:14 -07:00
tangxifan 7688c0570f [Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key 2021-09-21 15:08:08 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan 9074bffa68 [Tool] Support customized default value in pin constraint file 2021-07-01 23:43:19 -06:00
tangxifan fed975c52a [Tool] Add postfix removal support in write_io_mapping command 2021-06-18 16:13:50 -06:00
tangxifan db9bb9124e [Tool] Add report bitstream distribution command to openfpga shell 2021-05-07 11:41:25 -06:00
tangxifan 01b3a96e4b [Tool] Add report bitstream distribution functionality to architecture bitstream library 2021-05-07 11:22:01 -06:00
tangxifan 148da80869 [Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes 2021-04-24 14:53:29 -06:00
tangxifan 96ce6b545f [Tool] Patch repack to consider design constraints for pins that are not equivalent 2021-04-21 13:53:08 -06:00
tangxifan 5364b94cf8 [Tool] Update bitstream setting parser/writer to support interconnect-related syntax 2021-04-19 13:42:12 -06:00
tangxifan 0b49c22682 [Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks 2021-04-18 16:11:11 -06:00
tangxifan 6550ea3dfa [Tool] Rework pin constarint API to avoid expose raw data to judge for developers 2021-04-18 12:02:49 -06:00
tangxifan 6e9b24f9bf [Tool] Patch the invalid pin constraint net name 2021-04-17 19:56:30 -06:00
tangxifan d95a1e2776 [Tool] Encapulate search function in PinConstraint data structure 2021-04-17 17:31:55 -06:00
tangxifan d877a02534 [Tool] Patch the extended bitstream setting support on mode-select bits 2021-03-10 21:28:09 -07:00
tangxifan 85640a7403 [Tool] Extend bitstream setting to support mode bits overload from eblif file 2021-03-10 20:45:48 -07:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
tangxifan 73461971d2 [Tool] Bug fix for printing single-bit ports in Verilog netlists 2021-02-28 16:12:57 -07:00
tangxifan 7a5dd1bc02 [Tools] Patch circuit library for dummy circuit models without any ports 2021-02-24 10:36:48 -07:00
tangxifan b2984b46ee [Tool] Upgrade libopenfpga to support superLUT-related XML syntax 2021-02-09 21:15:57 -07:00
tangxifan faabdab815 [Tool] Remove redundant tab in bitstream setting writer 2021-02-01 18:04:21 -07:00
tangxifan d5b1cc5ec7 [Tool] Bug fix in parser for bitstream settings 2021-02-01 18:01:42 -07:00
tangxifan f102e84497 [Tool] Add bitstream setting file to openfpga library 2021-02-01 17:43:46 -07:00
tangxifan 3b7762ef85 [Lib] Now try to call undefined command will cause a error code to return 2021-01-24 17:44:51 -07:00
tangxifan a8158322ef [Tool] Bug fix in setting command execution status in OpenFPGA shell 2021-01-24 17:25:03 -07:00
tangxifan fd0e73a9bb [Tool] Enhance return code for openfpga shell 2021-01-24 14:48:27 -07:00
tangxifan 8cac3291cb [Tool] Add batch mode to openfpga shell execution 2021-01-24 14:33:58 -07:00
tangxifan 4cc8b08a6c [Tool] Add openfpga version display 2021-01-23 16:38:00 -07:00