tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
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2021-09-29 20:34:25 -07:00 |
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tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
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tangxifan
|
8f0ae937bc
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[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
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2021-09-29 16:57:49 -07:00 |
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tangxifan
|
ac6268d9ae
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[Engine] Bug fix on compilation errors
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2021-09-29 16:24:36 -07:00 |
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tangxifan
|
c5ae93f177
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[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
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2021-09-29 16:17:40 -07:00 |
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tangxifan
|
5da8f1db73
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[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
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2021-09-28 23:27:47 -07:00 |
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tangxifan
|
7723e00e6c
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[Engine] Adding the function that builds a shift register module for BL/WLs
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2021-09-28 22:49:24 -07:00 |
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tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
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2021-09-28 17:29:03 -07:00 |
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tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
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2021-09-28 11:53:38 -07:00 |
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tangxifan
|
e06ac11630
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[Engine] Bug fix
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2021-09-25 19:21:16 -07:00 |
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tangxifan
|
2de4a460a8
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[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
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2021-09-24 15:15:32 -07:00 |
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tangxifan
|
74ffc8578f
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[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
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2021-09-24 15:05:25 -07:00 |
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tangxifan
|
be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
|
18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
|
7e27c0caf3
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[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
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2021-09-23 16:16:39 -07:00 |
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tangxifan
|
962acda810
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[Engine] Bug fix in fabric key generation when computing configurable children
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2021-09-22 11:09:46 -07:00 |
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tangxifan
|
b0a471bdc9
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[Engine] Bug fix in outputting fabric key with coordinates
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2021-09-21 15:55:11 -07:00 |
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tangxifan
|
7688c0570f
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[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
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2021-09-21 15:08:08 -07:00 |
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tangxifan
|
c84c0d4a3f
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[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
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2021-09-20 17:07:26 -07:00 |
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tangxifan
|
36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
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2021-09-10 17:03:44 -07:00 |
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tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
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tangxifan
|
35c7b09888
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[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
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2021-09-09 15:23:29 -07:00 |
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tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
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tangxifan
|
1085e468e2
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[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
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tangxifan
|
475ce2c6d9
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[Engine] Upgrade fabric generator in support QL memory bank connections
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2021-09-05 17:49:01 -07:00 |
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tangxifan
|
ed80d6b3f4
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[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
|
2021-09-05 13:23:38 -07:00 |
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tangxifan
|
cf2e479d18
|
[Engine] Refactor the TopModuleNumConfigBits data structure
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2021-09-05 12:01:38 -07:00 |
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tangxifan
|
f75456e304
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[Engine] Update BL/WL estimation function for QL memory bank protocol
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2021-09-05 11:53:33 -07:00 |
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tangxifan
|
5759f5f35b
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[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
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2021-09-03 17:55:23 -07:00 |
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tangxifan
|
cbbf601edc
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[Tool] Fix a compiler warning due to uninitialized data structure
|
2021-06-18 16:20:13 -06:00 |
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tangxifan
|
c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
|
tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
|
2021-03-13 20:23:08 -07:00 |
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tangxifan
|
2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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tangxifan
|
e6091fb3ff
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[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
|
2021-02-18 21:56:30 -07:00 |
|
tangxifan
|
af4cc117fb
|
[Tool] bug fix in spypad lut
|
2021-02-09 22:53:18 -07:00 |
|
tangxifan
|
6a0f4f354f
|
[Tool] Support superLUT circuit model in core engine
|
2021-02-09 20:23:05 -07:00 |
|
tangxifan
|
c0da6b900a
|
[Tool] Bug fix in creating multi-bit clock port connections
|
2021-01-12 18:38:00 -07:00 |
|
tangxifan
|
65b2fe3ab7
|
[Tool] Bug fix in the global tile connection by considering all the subtiles
|
2021-01-10 11:52:38 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
cde26597ed
|
[Tool] Bug fix in scan chain builder calling
|
2021-01-04 18:45:47 -07:00 |
|
tangxifan
|
804b721a19
|
[Tool] Bug fix in the configuration chain connection builder
|
2021-01-04 17:41:29 -07:00 |
|
tangxifan
|
bfd305b5a5
|
[Tool] Patch the bug in finding data output ports for CCFF
|
2021-01-04 17:22:30 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
cb2bd2e31c
|
[Tool] Remove register ports for mini local encoders (1-bit data out)
|
2020-12-06 14:21:54 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
|
tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
|
tangxifan
|
3a708cff21
|
[Tool] Bug fix to enable nature fracturable LUT design
|
2020-11-25 23:01:18 -07:00 |