tangxifan
|
ab6f1a5461
|
add mux output ids for mux_graph
|
2019-08-26 21:21:50 -06:00 |
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tangxifan
|
c43fabb43c
|
developed verilog instance writer. refactoring on mux ongoing
|
2019-08-25 10:31:45 -06:00 |
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tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
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tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
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tangxifan
|
5e156dc725
|
minor fix for OSX and update travis using ccache to speed up compilation
|
2019-08-21 15:25:36 -06:00 |
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tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
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tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
69039aa742
|
developed subgraph extraction and start refactoring mux generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
bee070d7cc
|
start plug in MUX library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
893683fa95
|
start developing mux library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
153d506abb
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add graph-based mux decoding function
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2019-08-20 15:24:52 -06:00 |
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tangxifan
|
dcca9f4f0f
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finish mux graph builders
|
2019-08-20 15:24:52 -06:00 |
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tangxifan
|
638969c3c9
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adding mux graph data structures
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2019-08-20 15:24:52 -06:00 |
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tangxifan
|
0b8473e960
|
start developing graphs for muxes, with aims to simplify netlist and bitstream generation
|
2019-08-20 15:24:52 -06:00 |
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tangxifan
|
4cffd8ac2d
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keep route file updated with tileable rr_graph
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2019-08-13 15:37:42 -06:00 |
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tangxifan
|
cffdebd912
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bug fixed for the tileable RR graph generator for heterogeneous blocks
|
2019-07-11 21:02:09 -06:00 |
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tangxifan
|
65f696c1d7
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fix critical bugs in rectangle floorplan
|
2019-07-09 17:41:20 -06:00 |
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tangxifan
|
76fefdb876
|
bug fixing in Fc_in and be serious in the performance of rr_graph
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2019-07-05 16:23:15 -06:00 |
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tangxifan
|
c62762ce59
|
bug fixing in assign ipins to tracks using Fc_in
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2019-07-05 13:42:22 -06:00 |
|
tangxifan
|
64d8e9663a
|
minor fix to satisfy Fc_in and Fc_out
|
2019-07-05 13:13:35 -06:00 |
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tangxifan
|
3077efa74f
|
add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |
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tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
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2019-07-03 16:46:43 -06:00 |
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tangxifan
|
0c3e8bb70a
|
add a new option to the router to enable conversion of route_chan_width to be tileable
|
2019-07-03 12:11:48 -06:00 |
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tangxifan
|
4392c6bc3a
|
bug fixing in fpga_flow scripts and add more print-out message for VPR
|
2019-07-02 15:34:59 -06:00 |
|
tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
|
2019-07-02 10:00:02 -06:00 |
|
tangxifan
|
1332ba62e8
|
update tileable rr_graph generator to improve routability and also enable assoicated testing
|
2019-06-27 17:52:25 -06:00 |
|
tangxifan
|
15c536e9b4
|
minor fixing in printing the rr_node stats
|
2019-06-27 16:34:21 -06:00 |
|
tangxifan
|
42f85004b6
|
fix bugs in finding the ending SB of a rr_node
|
2019-06-26 14:13:41 -06:00 |
|
tangxifan
|
3c0ef2067d
|
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
|
2019-06-25 21:59:38 -06:00 |
|
tangxifan
|
4d3b5f12b4
|
fixed bugs for UNIVERSAL and WILTON switch blocks
|
2019-06-25 14:15:29 -06:00 |
|
tangxifan
|
785b560bd5
|
sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
|
2019-06-24 22:46:56 -06:00 |
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tangxifan
|
fd301eeb66
|
many bug fixing and now start improving the routability of tileable rr_graph
|
2019-06-24 17:33:29 -06:00 |
|
tangxifan
|
0d62661c71
|
bug fixing and spot critical bugs in directlist parser
|
2019-06-23 20:52:38 -06:00 |
|
tangxifan
|
cdd4af9c58
|
vpr likes the tileable rr_graph while fpga_x2p does not
|
2019-06-23 18:11:13 -06:00 |
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tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
|
tangxifan
|
2837f44df2
|
bug fixing for tileable rr_graph generator.
|
2019-06-22 20:41:06 -06:00 |
|
tangxifan
|
7c38b32eb1
|
keep bug fixing for tileable rr_graph generator
|
2019-06-21 22:51:11 -06:00 |
|
tangxifan
|
41954056ce
|
many bug fixing for tileable rr_graph generator. Still debugging
|
2019-06-21 17:58:46 -06:00 |
|
tangxifan
|
d48fd959a9
|
keep bug fixing for tileable rr_graph generator
|
2019-06-20 22:30:26 -06:00 |
|
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
|
tangxifan
|
baab9c4a21
|
basically finished the coding of tileable rr_graph generator. testing to go
|
2019-06-20 18:17:07 -06:00 |
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tangxifan
|
2f15d2d13c
|
keep developing tileable rr_graph, track2ipin and opin2track to go
|
2019-06-19 21:30:16 -06:00 |
|
tangxifan
|
ba15358564
|
developing ipin2track mapping for tiles
|
2019-06-18 18:06:21 -06:00 |
|
tangxifan
|
9ca1b42f4c
|
developing switch block pattern for tileable routing architecture
|
2019-06-18 16:52:42 -06:00 |
|
tangxifan
|
352c97302b
|
start building object GSB graph
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2019-06-17 22:10:30 -06:00 |
|
tangxifan
|
f4191315da
|
use rr_gsb to build edges of rr_graph
|
2019-06-17 18:01:45 -06:00 |
|
tangxifan
|
51ff150a77
|
bug fixing in tileable rr_graph generator
|
2019-06-17 10:16:08 -06:00 |
|
tangxifan
|
0d14fef53e
|
bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
|
2019-06-16 23:02:18 -06:00 |
|
tangxifan
|
1af3b5ef55
|
set chan_rr_nodes in tileable rr_graph builder
|
2019-06-16 14:23:19 -06:00 |
|
tangxifan
|
8c9cc003ea
|
developing routing track rr_node set up in tileable routing architecture
|
2019-06-15 18:11:08 -06:00 |