tangxifan
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73e9006372
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add arch file with spy pads
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2020-04-22 12:56:09 -06:00 |
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tangxifan
|
9fb8971281
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add FPGA arch with spypads to portofilo
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2020-04-22 11:12:28 -06:00 |
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tangxifan
|
f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
|
98878f474b
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light change on arch file to accelerate mcnc big20 run
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2020-04-19 12:03:31 -06:00 |
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tangxifan
|
95863e996a
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minor update on arch to use auto layout sizing
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2020-04-18 18:43:56 -06:00 |
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tangxifan
|
2f3a36ee81
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update timing and rename the arch file
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2020-04-18 18:39:47 -06:00 |
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tangxifan
|
7ce34be175
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update sample architecture timing
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2020-04-17 22:06:06 -06:00 |
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tangxifan
|
2ea4b8a2a2
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add more flagship architectures
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2020-04-17 19:12:27 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
|
214d98fbcd
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add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
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tangxifan
|
148cc74d6a
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add io test cases to Travis CI
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2020-04-12 15:01:47 -06:00 |
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tangxifan
|
da5af8f0e0
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try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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tangxifan
|
600a48edc7
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add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
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tangxifan
|
68fd296e14
|
add more test vpr architecture to regression tests
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2020-04-12 12:49:16 -06:00 |
ganeshgore
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eb3b02277a
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Added XML and benchmarks for testing
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2020-04-06 00:32:06 -06:00 |
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tangxifan
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b219b096ee
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hotfix on removing dangling inputs from GSB, which are CLB direct output
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2020-03-08 13:54:49 -06:00 |
AurelienUoU
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85c9f26a9f
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Update documentation about cmake version and graphical interface
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2020-01-22 20:46:49 -07:00 |
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tangxifan
|
d391983e8c
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passing regression test on dpram benchmarks
|
2019-11-07 14:57:46 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
tangxifan
|
a308a13d7c
|
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
|
2019-11-05 15:41:59 -07:00 |
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tangxifan
|
4398cffaaa
|
single mode is working, multi-mode is under debugging
|
2019-10-29 22:32:36 -06:00 |
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tangxifan
|
5cb3717433
|
add single mode test case to regression test. debugging now
|
2019-10-28 15:57:17 -06:00 |
|
AurelienUoU
|
cc0bfdd548
|
Add testcase in regression test for architecture with 1 IO cell/IO block
|
2019-09-20 10:27:26 -06:00 |
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tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
tangxifan
|
5abbfd6a0f
|
add tileable routing to regression test
|
2019-09-16 20:45:02 -06:00 |
|
tangxifan
|
d2d750a15c
|
debugged rram mux branch Verilog generation
|
2019-09-02 16:21:29 -06:00 |
|
tangxifan
|
94538b5062
|
add more testing architecture
|
2019-08-27 18:44:58 -06:00 |
|
tangxifan
|
3fb3082447
|
add more tests
|
2019-08-23 14:10:01 -06:00 |
|
Ganesh Gore
|
52d6a9e979
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-23 13:41:29 -06:00 |
|
Ganesh Gore
|
28dde899db
|
Updated Architecture Template
|
2019-08-23 12:44:45 -06:00 |
|
tangxifan
|
520630c5e2
|
add more testing tasks
|
2019-08-23 10:16:52 -06:00 |
|
Ganesh Gore
|
5116aa2ae1
|
Added architecture and replaced variables
|
2019-08-19 19:02:50 -06:00 |
|
Ganesh Gore
|
66bb8a5e4b
|
Updated RRAM architecture file
|
2019-08-17 02:20:04 -06:00 |
|
Ganesh Gore
|
7bfc48b8e4
|
Moved spice and verilog netlist folder location
|
2019-08-17 01:49:49 -06:00 |
|
Ganesh Gore
|
9ab57d1b2e
|
Added fpga_flow script - Working Yosys
|
2019-08-09 16:49:05 -06:00 |
|
Ganesh Gore
|
b82369dd96
|
Added first draft of fpga_task script
|
2019-08-09 00:17:06 -06:00 |