tangxifan
|
b83319bf14
|
[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
|
2020-08-23 13:48:22 -06:00 |
|
tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
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tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
|
tangxifan
|
2712c354a9
|
now physical pb_port binding support multiple ports
|
2020-08-18 12:38:56 -06:00 |
|
tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
|
2020-07-24 19:51:32 -06:00 |
|
tangxifan
|
6d046efc52
|
add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
|
2020-07-24 16:25:27 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
de4586217f
|
now device binding is not mandatory for circuit models
|
2020-07-14 12:04:22 -06:00 |
|
tangxifan
|
e2b492f184
|
add circuit model tech binding
|
2020-07-13 20:35:10 -06:00 |
|
tangxifan
|
f081cef495
|
add fabric key library
|
2020-06-12 00:07:04 -06:00 |
|
tangxifan
|
58807bfcb3
|
remove simulation settings from openfpga arch data structure
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
15f087598c
|
split simulation settings to a separated XML file
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
62c506182c
|
start developing frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
6eb125ec2a
|
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
|
2020-04-06 14:09:52 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
|
2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
59c13550e0
|
add direct annotation with inter-column/row syntax
|
2020-02-14 17:40:59 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
|
2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
24b180b298
|
change the mode bit storage in annotation data structure from string to vector of integers
|
2020-01-29 11:59:20 -07:00 |
|
tangxifan
|
7d4b07421d
|
finish XML parser and writer for pb_type annotation
|
2020-01-26 15:54:49 -07:00 |
|
tangxifan
|
1cba141dd0
|
add pb parser and support XML parsing for pb type name in full hiearchy
|
2020-01-26 11:52:58 -07:00 |
|
tangxifan
|
cd3565cf53
|
complete the XML parser for pb_type annotation
|
2020-01-26 10:56:57 -07:00 |
|
tangxifan
|
a9f03ce21b
|
add XML attribute parsing for physical and operating pb_type annotation
|
2020-01-26 10:19:47 -07:00 |
|
tangxifan
|
bafd866cfc
|
start developing XML parser for pb_type annotation
|
2020-01-25 21:19:08 -07:00 |
|
tangxifan
|
b6f96e5a8f
|
add method functions to pb_type annotation
|
2020-01-25 20:46:21 -07:00 |
|
tangxifan
|
9b4b6ae083
|
rename pb_annotation and move it to openfpga namespace
|
2020-01-25 18:17:00 -07:00 |
|
tangxifan
|
f834954698
|
start developing the pb_type annotation
|
2020-01-25 18:14:38 -07:00 |
|
tangxifan
|
655f84b00e
|
add write_openfpga_arch command to openfpga shell
|
2020-01-23 20:58:15 -07:00 |
|
tangxifan
|
a03f8aa346
|
add profiling for read arch
|
2020-01-23 20:12:30 -07:00 |
|
tangxifan
|
07994d424c
|
add XML parser and writer for direct connection
|
2020-01-19 15:00:19 -07:00 |
|
tangxifan
|
10336cbe67
|
add XML parser and writer for routing circuit definition for OpenFPGA architecture
|
2020-01-19 14:44:27 -07:00 |
|
tangxifan
|
ebe46d15a9
|
add XML parser, writer and linker for configuration protocol data structure
|
2020-01-18 21:19:20 -07:00 |
|
tangxifan
|
9693c3a12d
|
add XML writer for simulation setting object
|
2020-01-18 16:41:42 -07:00 |
|
tangxifan
|
bc3130d196
|
add XML parser for simulation setting
|
2020-01-18 15:40:20 -07:00 |
|
tangxifan
|
2a902c7e55
|
add mutators to simulation setting data structure
|
2020-01-18 14:07:37 -07:00 |
|
tangxifan
|
0de9908d52
|
add accessors to simulation setting data structure
|
2020-01-18 12:51:25 -07:00 |
|
tangxifan
|
ab1b1b7e02
|
add XML writer for technology library
|
2020-01-17 20:02:56 -07:00 |
|
tangxifan
|
8f2936af54
|
finish XML parser for technology library
|
2020-01-17 17:43:55 -07:00 |
|
tangxifan
|
e54760c677
|
add XML parsing for transistors and RRAM parameters in technology library
|
2020-01-17 17:32:42 -07:00 |
|
tangxifan
|
d48a888804
|
add XML parsing for design parameters in technology library
|
2020-01-17 17:22:09 -07:00 |
|
tangxifan
|
de0bcc96fb
|
add missing file about XML parsers for technology library
|
2020-01-17 17:16:32 -07:00 |
|
tangxifan
|
d58186507c
|
add XML parsing for device model library settings
|
2020-01-17 17:15:58 -07:00 |
|
tangxifan
|
88a96673e3
|
rename some methods in technology library and start building associated XML parser
|
2020-01-17 16:44:57 -07:00 |
|
tangxifan
|
d4b5171fa2
|
add comments to technology library
|
2020-01-17 15:31:44 -07:00 |
|
tangxifan
|
313922f03f
|
add internal linker to technology library
|
2020-01-17 15:04:00 -07:00 |
|
tangxifan
|
edaaa00c1d
|
added mutators for technology library
|
2020-01-17 14:46:09 -07:00 |
|
tangxifan
|
6b703a4fc5
|
add accessors to technology library data structure
|
2020-01-17 13:34:32 -07:00 |
|
tangxifan
|
771f2d9c37
|
developing data structure TechnologyLibrary to store technology-related information
|
2020-01-17 10:17:15 -07:00 |
|
tangxifan
|
aa070b2a41
|
further clean-up sample arch.xml
|
2020-01-17 09:38:35 -07:00 |
|
tangxifan
|
95edd3c091
|
clean up the sample arch
|
2020-01-16 20:52:47 -07:00 |
|
tangxifan
|
f7a7c56366
|
move OpenFPGAArch to openfpga namespace
|
2020-01-16 20:22:56 -07:00 |
|
tangxifan
|
d6adfa0821
|
add XML parsing for delay matrix and wire parasitics for circuit library
|
2020-01-16 20:14:39 -07:00 |
|
tangxifan
|
2e0ce78054
|
add XML writing for buffers in circuit library
|
2020-01-16 17:21:41 -07:00 |
|
tangxifan
|
9ba42cd540
|
add XML writer for circuit ports
|
2020-01-16 16:05:11 -07:00 |
|
tangxifan
|
0304d723c0
|
add XML writer for design technology of a circuit model
|
2020-01-16 14:45:41 -07:00 |
|
tangxifan
|
3ace7f8ef7
|
move generic data structures to openfpgautil library
|
2020-01-16 13:26:55 -07:00 |
|
tangxifan
|
d232391250
|
developed XML writer for circuit library and start porting functions to openfpgautil library
|
2020-01-16 12:32:29 -07:00 |
|
tangxifan
|
e282f813bc
|
rename circuit settings to openfpga arch and update sample architecture
|
2020-01-15 20:28:04 -07:00 |
|
tangxifan
|
264dc8458d
|
add XML parsing for delay matrix in circuit model
|
2020-01-15 20:21:53 -07:00 |
|
tangxifan
|
602d0bde4c
|
add XML parsing for wire parasitics in circuit model
|
2020-01-15 19:54:57 -07:00 |
|
tangxifan
|
999c364b25
|
added XML parsing for circuit model ports
|
2020-01-15 17:29:49 -07:00 |
|
tangxifan
|
c20e1d48d2
|
added XML parsing for pass-gate-logic in circuit models
|
2020-01-15 15:49:02 -07:00 |
|
tangxifan
|
a9b122d584
|
add XML parsing for buffer models in circuit library
|
2020-01-15 15:27:49 -07:00 |
|
tangxifan
|
35d6c9661b
|
Finish the first version of XML parser for design technology of circuit models
|
2020-01-14 16:24:27 -07:00 |
|
tangxifan
|
5937ffc809
|
add XML parsing for buffer/pass-gate-logic -related properties
|
2020-01-14 15:44:24 -07:00 |
|
tangxifan
|
56113e1aab
|
adding XML parsing for design tech of circuit model
|
2020-01-14 14:10:00 -07:00 |
|
tangxifan
|
2692d0fc35
|
adding XML parsing for SPICE and Verilog netlist for each circuit model
|
2020-01-14 08:45:27 -07:00 |
|
tangxifan
|
82d83ddceb
|
reorganized the read XML openfpga arch
|
2020-01-14 08:33:48 -07:00 |
|
tangxifan
|
ca3ca14cc7
|
fixed bugs in XML when parsing circuit model types
|
2020-01-13 21:52:13 -07:00 |
|
tangxifan
|
db503ffebf
|
add openfpga read xml executable and start min unit test
|
2020-01-13 21:05:58 -07:00 |
|
tangxifan
|
d6c69ea7c6
|
developing XML parser for circuit model name and type
|
2020-01-12 23:45:51 -07:00 |
|
tangxifan
|
e2f641fdb3
|
add example architecture for openfpga and developing XML parser
|
2020-01-12 22:39:38 -07:00 |
|
tangxifan
|
2e986608ba
|
initial commit on parser for reading openfpga arch xml
|
2020-01-12 21:33:28 -07:00 |
|
tangxifan
|
48ecb6e48b
|
immigrate XML parser for circuit_lib to library readarchopenfpga
|
2020-01-12 18:11:00 -07:00 |