tangxifan
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3b42fe94d6
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[Architecture] Update external bitstream file
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2020-09-24 14:41:44 -06:00 |
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tangxifan
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08838c4957
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[Regression Test] Deploy new configuration chain test cases to CI
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2020-09-24 14:36:39 -06:00 |
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tangxifan
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7fbccdd102
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[Regression Tests] Add test cases for configuration chain using different DFF cells
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2020-09-24 14:34:12 -06:00 |
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tangxifan
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178afb3c7f
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[Architecture] Add configuration chain architectures using different DFF cells
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2020-09-24 14:23:27 -06:00 |
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tangxifan
|
98d88dc686
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[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
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tangxifan
|
efad0402c2
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[Regression Test] Bug fix for CI errors
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2020-09-24 13:55:41 -06:00 |
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tangxifan
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e7906899dd
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[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
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2020-09-24 13:53:12 -06:00 |
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tangxifan
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e832d806c7
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[Architecture] Add DFF Verilog netlist using standard naming convention
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2020-09-24 13:50:59 -06:00 |
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tangxifan
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1b13e8ecb1
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[Architecture] Bug fix in the SRAM Verilog
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2020-09-24 12:26:13 -06:00 |
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tangxifan
|
9d9cf6ee71
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[Regression Test] Deploy new tests to CI
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2020-09-24 12:20:18 -06:00 |
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tangxifan
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ffd1a72d22
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[Architecture] Add regression tests for the frame-based configuration using reset and set signals
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2020-09-24 12:18:26 -06:00 |
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tangxifan
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539bb617f9
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[Architecture] Add reset test case for frame based configuration
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2020-09-24 12:17:18 -06:00 |
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tangxifan
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2add0406a7
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[Architecture] Update architecture files for new latch naming
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2020-09-24 12:14:03 -06:00 |
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tangxifan
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fde15c4f88
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[Regression Test] Add test for fast memory bank configuration using set signals
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2020-09-24 12:13:35 -06:00 |
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tangxifan
|
7238a2be03
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[Architecture] Merge latch Verilog HDL to a unique file
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2020-09-24 11:02:01 -06:00 |
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tangxifan
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48083d2276
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[Regression Test] Adapt fast memory bank test case
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2020-09-24 10:32:03 -06:00 |
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tangxifan
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83971bba41
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[Architecture] Update cell ports for native SRAM cell
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2020-09-24 10:31:31 -06:00 |
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tangxifan
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e454467799
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[Regression Test] Deploy memory bank test cases to CI
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2020-09-24 10:26:10 -06:00 |
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tangxifan
|
186f00edfc
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[Regression Test] Add test cases for memory bank using different SRAM cells
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2020-09-24 10:25:03 -06:00 |
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tangxifan
|
56c9aab190
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[Architecture] Add architecture to use different SRAM cells for memory bank
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2020-09-24 10:15:08 -06:00 |
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tangxifan
|
6bb30ab33c
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[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support
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2020-09-24 10:02:51 -06:00 |
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tangxifan
|
70a8c6dc29
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[Regression Test] Add test case using active-low set to CI
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2020-09-23 23:07:19 -06:00 |
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tangxifan
|
10b6e1dc0d
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[Architecture] bug fix for active-low
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2020-09-23 23:06:46 -06:00 |
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tangxifan
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5b0d451f0f
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[Regression Test] Add test case for configurable latch with active-low set
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2020-09-23 23:04:10 -06:00 |
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tangxifan
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5d60b4ef8c
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[Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set
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2020-09-23 23:02:49 -06:00 |
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tangxifan
|
8e780635df
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[Regression Test] Rename test case in CI
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2020-09-23 22:59:46 -06:00 |
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tangxifan
|
d0cef68242
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[Regression test] Add test case for using resetb
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2020-09-23 22:58:59 -06:00 |
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tangxifan
|
c7fc0178b0
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[Architecture] Rename to be consist with other architectures
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2020-09-23 22:57:06 -06:00 |
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tangxifan
|
07198f6396
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[Regression Test] Deploy smart configuration tests to CI
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2020-09-23 22:08:30 -06:00 |
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tangxifan
|
707300a6e4
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[Architecture] Bug fix for using both reset and set architecture
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2020-09-23 22:07:40 -06:00 |
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tangxifan
|
77a1f99564
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[Architecture] Bug fix for architecture using set only
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2020-09-23 22:04:24 -06:00 |
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tangxifan
|
46b12611a9
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[OpenFPGA Tool] Bug fix for smart fast configuration
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2020-09-23 22:04:07 -06:00 |
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tangxifan
|
fcf1ff418f
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[Architecture] Add Verilog for SRAM using set/reset
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2020-09-23 21:53:38 -06:00 |
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tangxifan
|
73e59d67af
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[Architecture] Add test case for fast configuration using set signals
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2020-09-23 21:50:23 -06:00 |
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tangxifan
|
349aa79069
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[Regression test] Add test case for smart fast configuration
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2020-09-23 21:49:38 -06:00 |
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tangxifan
|
9331ef941d
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[Architecture] Add architecture that use both set and reset signals
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2020-09-23 21:46:04 -06:00 |
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tangxifan
|
7591060fbd
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[Architecture] Add configurable latch Verilog designs and assoicated architectures
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2020-09-23 21:45:06 -06:00 |
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tangxifan
|
8fa4fa1125
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[Architecture] Add openfpga architecture using set signals for configurable latch
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2020-09-23 21:39:31 -06:00 |
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tangxifan
|
154c9045f6
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[OpoenFPGA Tool] Bug fix for smart fast configuration
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2020-09-23 21:38:42 -06:00 |
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tangxifan
|
c2c37d7555
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[OpenFPGA Tool] Add more print-out for smart fast configuration
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2020-09-23 21:34:23 -06:00 |
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tangxifan
|
f57fd273af
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[Documentation] Update documentation for smart fast configuration
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2020-09-23 21:28:06 -06:00 |
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tangxifan
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a3abf81afe
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[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
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2020-09-23 21:25:06 -06:00 |
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tangxifan
|
709a20a349
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[Regression Test] Deploy new test to CI
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2020-09-23 20:45:19 -06:00 |
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tangxifan
|
05c2e652a4
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[Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol
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2020-09-23 20:44:06 -06:00 |
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tangxifan
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2869eae8a9
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[Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol
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2020-09-23 20:43:15 -06:00 |
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tangxifan
|
fc60b18191
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[Architecture] Now a regular flip-flop can be used in frame-based configuration
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2020-09-23 20:41:49 -06:00 |
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tangxifan
|
8b8ce22fd1
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[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
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2020-09-23 20:37:28 -06:00 |
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tangxifan
|
3d234d840b
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[Documentation] Update documentation for the edge triggered attribute
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2020-09-23 20:31:11 -06:00 |
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tangxifan
|
064678fe32
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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tangxifan
|
8e4e66038a
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[Architecture] Bug fix for standalone memory
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2020-09-23 19:32:48 -06:00 |