tangxifan
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dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
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e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
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8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
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9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
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e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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tangxifan
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3aeea724de
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[Documentation] Update for new options in fpga-verilog
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2020-10-12 12:36:24 -06:00 |
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tangxifan
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1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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5efe1ae77d
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Merge pull request #106 from LNIS-Projects/dev
Documentation update
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2020-10-10 23:16:37 -06:00 |
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tangxifan
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ccaa697e5a
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[Documentation] Add links to technical features to examples
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2020-10-10 22:40:37 -06:00 |
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tangxifan
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ea3a1b785c
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[Documentation] Fix the path to OpenFPGA logo in the README
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2020-10-10 21:44:18 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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8493345b52
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Merge pull request #105 from LNIS-Projects/dev
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
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2020-10-10 21:43:02 -06:00 |
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tangxifan
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b8c20959b6
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[Regression test] Add new test case to CI
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2020-10-10 20:29:00 -06:00 |
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tangxifan
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82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
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d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
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721bcce373
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[Tool] Change analysis SDC file name to track netlist name
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2020-10-10 17:43:35 -06:00 |
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tangxifan
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5fece94e7c
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Merge pull request #103 from lukefahr/doc_fix
Docs: Updated note to enable VPR's GUI
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2020-10-08 15:56:44 -06:00 |
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tangxifan
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521accdc88
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Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
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tangxifan
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7b12c28e4f
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Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
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Andrew Lukefahr
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00295a003f
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Docs: Updated note to enable VPR's GUI
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2020-10-06 20:47:43 -04:00 |
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Andrew Lukefahr
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d68427e47b
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Fixed blif formatting bug
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2020-10-06 20:46:50 -04:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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5464d9f2c4
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Merge pull request #101 from LNIS-Projects/dev
Documentation Update to Include Technical Features
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2020-10-06 13:55:10 -06:00 |
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tangxifan
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800931c840
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[Documentation] Add configuration protocol to technical highlights
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2020-10-06 12:16:15 -06:00 |
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tangxifan
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56ab63d939
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[Documentation] Fix format in table
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2020-10-06 12:02:15 -06:00 |
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tangxifan
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c8339fc473
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[Documentation] Typo fix
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2020-10-06 12:00:30 -06:00 |
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tangxifan
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113708c68f
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[Documentation] Reorganization the overview part by adding technical highlights
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2020-10-06 11:56:10 -06:00 |
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tangxifan
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02e21d115b
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[Documentation] Update 3-rd party tool version requirements
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2020-10-06 10:00:12 -06:00 |
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tangxifan
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7d5dbab304
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Merge pull request #100 from lukefahr/bug_fixes
Edits to enable basic run_fpga_flow.py
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2020-10-02 10:14:30 -06:00 |
|
Andrew Lukefahr
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2d92a1f1af
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Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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7a139c91a1
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Merge pull request #98 from LNIS-Projects/dev
Support of multiple regions for configuration chain
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2020-09-29 17:34:43 -06:00 |
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tangxifan
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67300af987
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[Documentation] Update motivation with new set of figures
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2020-09-29 16:52:16 -06:00 |
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tangxifan
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6817c045c2
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[Documentation] Update tutorial about tooling
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2020-09-29 16:24:52 -06:00 |
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tangxifan
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639d57016b
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[Documentation] Update documentation about the multi-region configuration
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2020-09-29 15:55:42 -06:00 |
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tangxifan
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d4d02ab16a
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[Regression Test] Move fabric key tests to basic tests
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2020-09-29 14:22:23 -06:00 |
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tangxifan
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ff6570df9d
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[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
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2020-09-29 14:19:40 -06:00 |
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tangxifan
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4f00d310d3
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[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
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tangxifan
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02ea639959
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[Regression Test] Add test for fabric key based on multiple region
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2020-09-29 14:13:38 -06:00 |
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tangxifan
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462886fb5f
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[Documentation] Update documentation for the multiple region support on configuration chain
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2020-09-29 14:02:03 -06:00 |
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tangxifan
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6e8ebd7979
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[Regression Tests] Deploy multi-region test cases to CI
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2020-09-29 13:57:31 -06:00 |
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tangxifan
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a0d1d68402
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[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
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2020-09-29 13:53:41 -06:00 |
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tangxifan
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d5c7411399
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[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
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2020-09-29 13:50:31 -06:00 |
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tangxifan
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5be5835b71
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[Regression Test] Add multiple region configuration chain test case
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2020-09-29 13:48:39 -06:00 |
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tangxifan
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23449dc5c3
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[Architecture] Add multiple region configuration chain architecture
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2020-09-29 13:46:40 -06:00 |
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tangxifan
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e0d7bcfa11
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[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
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2020-09-29 12:49:32 -06:00 |
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tangxifan
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e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
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tangxifan
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180d72f3e5
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[Tool] Add regions to fabric bitstream
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2020-09-28 21:04:08 -06:00 |
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tangxifan
|
e179a58b15
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[OpenFPGA Tool] Bug fix for long runtime
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2020-09-28 20:42:18 -06:00 |
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tangxifan
|
47f3c79927
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[OpenFPGA Tool] Bug fix in module manager due to configurable regions
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2020-09-28 19:08:19 -06:00 |
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tangxifan
|
f93d46a870
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[OpenFPGA Tool] Add multiple configuration chain support in top module builder
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2020-09-28 19:03:19 -06:00 |
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tangxifan
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552dddffd0
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[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |