AurelienAlacchi
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00fc3d7622
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Merge pull request #217 from lnis-uofu/dev
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
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2021-02-05 09:53:28 -07:00 |
tangxifan
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9b5c64f35f
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[Doc] Update documentation about disable_packing syntax
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2021-02-04 16:41:24 -07:00 |
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tangxifan
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d83158654c
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[Doc] Add a draft documentation about the bitstream setting
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2021-02-01 22:33:17 -07:00 |
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tangxifan
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0e16638dc2
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[Doc] Update documentation about the changes on activity files
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2021-01-29 11:49:07 -07:00 |
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tangxifan
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78ad9cd000
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[Doc] Add version command/option to documentation
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2021-01-27 16:06:45 -07:00 |
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tangxifan
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d53d3963d4
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[Doc] Broken link fix in config protocol documentation
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2021-01-26 14:05:11 -07:00 |
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tangxifan
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9fefe1502f
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[Doc] Typo fix on write_fabric_key option
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2021-01-25 15:18:16 -07:00 |
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tangxifan
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dd0680246a
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[Doc] Typo fix on fabric key command
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2021-01-25 14:12:40 -07:00 |
ganeshgore
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1ba7e0663f
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Merge pull request #176 from lnis-uofu/dev
Documentation Formatting
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2021-01-24 21:11:49 -07:00 |
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tangxifan
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e18c533657
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[Doc] Add new openfpga shell command to documentation
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2021-01-24 14:48:56 -07:00 |
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tangxifan
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815468ac65
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[Doc] Add shortcut to call pin constraint option to documentation
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2021-01-20 09:20:51 -07:00 |
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tangxifan
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977ff52cb1
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[Doc] Format openfpga command documentation by using option views
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2021-01-19 20:26:38 -07:00 |
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tangxifan
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e9dc708d66
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[Doc] Group file format documentation into a unified section
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2021-01-19 19:44:44 -07:00 |
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tangxifan
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ac8c63553a
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[Doc] Add file format index file
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2021-01-19 18:07:53 -07:00 |
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tangxifan
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fbb5c0cf8f
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[Doc] Add pin constraints to documentation
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2021-01-19 18:04:45 -07:00 |
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tangxifan
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c7f02601ab
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[Doc] Add repack design constraints to documentation
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2021-01-17 12:59:46 -07:00 |
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tangxifan
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c4d3e7c50c
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[Doc] Update documentation for the new XML syntax in simulation settings
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2021-01-15 12:30:26 -07:00 |
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tangxifan
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0c808bec41
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[Doc] Add clarification for defining multi-bit global tile ports
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2021-01-09 20:00:16 -07:00 |
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tangxifan
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2324edc522
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[Doc] Update documentation for upgraded tile annotation
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2021-01-09 18:55:16 -07:00 |
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tangxifan
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226f6b8d6d
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
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tangxifan
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406edeec89
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[Doc] Typo fix
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2020-12-04 15:07:02 -07:00 |
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tangxifan
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4fe190fa7e
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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tangxifan
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8350b0f911
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[Doc] Update documentation about default value definition in tile annotation
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2020-12-02 17:08:34 -07:00 |
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tangxifan
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cc0114459a
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[Doc] Enrich examples for LUT circuit models
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2020-11-26 13:03:12 -07:00 |
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tangxifan
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62e804215b
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[Doc] Add svg figures for LUT examples
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2020-11-26 12:35:39 -07:00 |
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tangxifan
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b857135f4e
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[Doc] Add clarification about which cells are applicable for signal initialization
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2020-11-23 15:19:15 -07:00 |
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tangxifan
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2b9a97729e
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[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
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2020-11-23 15:09:47 -07:00 |
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tangxifan
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fd0e6814ea
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[Doc] Update documentation about the pre-processing flags
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2020-11-22 20:33:15 -07:00 |
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tangxifan
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f6126d1ed6
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[Doc] Add illustrative example to diff between global ports definitions
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2020-11-12 09:24:39 -07:00 |
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tangxifan
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bc43c876b0
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[Doc] Update documentation for the rules in global port definition for tile ports
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2020-11-11 14:10:11 -07:00 |
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tangxifan
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2c269c532a
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[Doc] Update doc for the global port definition using physical tile port
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2020-11-10 20:48:28 -07:00 |
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tangxifan
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056b7c0c79
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[Doc] Update documentation about CCFF circuit model examples
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2020-11-06 12:22:22 -07:00 |
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tangxifan
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849ecc7fc0
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[Doc] Add notes for using the is_data_io syntax
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2020-11-05 09:30:19 -07:00 |
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tangxifan
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9bce2f3818
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[Doc] Update documentation for new XML syntax "is_data_io"
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2020-11-05 09:28:46 -07:00 |
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tangxifan
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be7f7592ae
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[Doc] Update documentation about don't care bit in frame address
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2020-10-30 22:13:28 -06:00 |
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tangxifan
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7e940980e1
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[Doc] Update documentation about configuration regions for frame-based protocol
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2020-10-30 21:52:01 -06:00 |
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tangxifan
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c2c384e24b
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[Doc] update documentation about memory bank definition
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2020-10-29 17:04:25 -06:00 |
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tangxifan
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3aeea724de
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[Documentation] Update for new options in fpga-verilog
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2020-10-12 12:36:24 -06:00 |
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tangxifan
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ccaa697e5a
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[Documentation] Add links to technical features to examples
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2020-10-10 22:40:37 -06:00 |
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tangxifan
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56ab63d939
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[Documentation] Fix format in table
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2020-10-06 12:02:15 -06:00 |
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tangxifan
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113708c68f
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[Documentation] Reorganization the overview part by adding technical highlights
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2020-10-06 11:56:10 -06:00 |
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tangxifan
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67300af987
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[Documentation] Update motivation with new set of figures
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2020-09-29 16:52:16 -06:00 |
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tangxifan
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639d57016b
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[Documentation] Update documentation about the multi-region configuration
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2020-09-29 15:55:42 -06:00 |
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tangxifan
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462886fb5f
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[Documentation] Update documentation for the multiple region support on configuration chain
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2020-09-29 14:02:03 -06:00 |
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tangxifan
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94a1324f05
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[Documentation] Remove deprecated XML syntax
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2020-09-26 14:31:57 -06:00 |
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tangxifan
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f57fd273af
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[Documentation] Update documentation for smart fast configuration
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2020-09-23 21:28:06 -06:00 |
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tangxifan
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3d234d840b
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[Documentation] Update documentation for the edge triggered attribute
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2020-09-23 20:31:11 -06:00 |
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tangxifan
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7a2502ddf9
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[documentation] add more guidelines about the vpr-openfpga architecture annotation
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2020-09-02 22:47:14 -06:00 |
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tangxifan
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ac8e937a50
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[Documentation] Update for default circuit model rules
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2020-08-23 14:08:38 -06:00 |
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tangxifan
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fb5a5a2448
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[documentation] remove the limitation on through channels
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2020-08-19 20:12:49 -06:00 |