Commit Graph

17 Commits

Author SHA1 Message Date
tangxifan e1a7a2895a simulation ini file name can be customizable 2019-11-02 09:59:34 -06:00
tangxifan d5d7450ce7 make simulation ini writing as an option 2019-11-02 09:46:12 -06:00
tangxifan c7526cb43c memory sanitized 2019-08-13 14:19:40 -06:00
Baudouin Chauviere 4ca0967453 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-09 14:35:51 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan 548242b368 plug-in tileable rr generator which can be enable by a XML property 2019-06-20 21:06:26 -06:00
tangxifan ca363da30c add options to specify output directory of SB XML 2019-05-28 15:19:10 -06:00
tangxifan a3c3f2b892 developing compact routing hierarchy 2019-05-08 20:49:21 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
Aur??Lien ALACCHI 0580d8243f Add Autochek testbench option 2018-12-08 17:19:12 -07:00
Aur??Lien ALACCHI 9a8c7b391a Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
tangxifan c67ba5f58a clean up codes 2018-09-27 14:26:08 -06:00
tangxifan d683134b12 rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00