Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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Ganesh Gore
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bcbcd463fe
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Added pending runs in log
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2019-09-06 11:48:13 -04:00 |
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Ganesh Gore
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702a7683a8
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Ensure strict exit of fpga_flow on error
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2019-09-05 10:23:35 -06:00 |
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Ganesh Gore
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f862ac02c8
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Restored OSX header installation [ci skip]
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2019-09-03 11:05:42 -06:00 |
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Ganesh Gore
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37439578db
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Removed OSX package installer to test
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2019-09-03 10:32:14 -06:00 |
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Ganesh Gore
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48ec1eefcd
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Added fpga_task cmd options in doc [ci skip]
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2019-09-02 02:45:05 -06:00 |
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Ganesh Gore
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241b001282
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Added openfpga_task doc
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2019-09-01 22:15:53 -06:00 |
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Ganesh Gore
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0439476abe
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Removed OSX allowed failure from travis
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2019-09-01 00:08:14 -06:00 |
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Ganesh Gore
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ac8cc230ed
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Added Exit on fail option to travis task run
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2019-08-31 22:58:07 -06:00 |
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Ganesh Gore
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be6b11304e
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Added travis fold for Python Task [ci skip]
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2019-08-31 22:36:18 -06:00 |
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Ganesh Gore
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ad4c688206
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Added print for JobID to architecture mapping
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2019-08-31 22:04:57 -06:00 |
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Ganesh Gore
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f4e99c150a
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resolve missing variable bug
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2019-08-31 21:55:32 -06:00 |
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Ganesh Gore
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3d4f7f66fd
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Updated to run with python3
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2019-08-31 21:42:31 -06:00 |
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Ganesh Gore
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d13c6a32ff
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Test travis cache
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2019-08-31 20:45:54 -06:00 |
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Ganesh Gore
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31c4d40e66
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Updated cache directory variable
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2019-08-31 20:00:44 -06:00 |
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Ganesh Gore
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32d47d6b8b
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Update document + Travis cache check
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2019-08-31 16:13:47 -06:00 |
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Ganesh Gore
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3ce63e6163
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Added abc and yosys cache in travis
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2019-08-31 15:26:14 -06:00 |
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Ganesh Gore
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06c0dbb328
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Added docuementation for fpga_flow
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2019-08-31 15:19:34 -06:00 |
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Ganesh Gore
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02137805c7
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Added python version check in flow and task scripts
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2019-08-29 22:14:30 -06:00 |
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Ganesh Gore
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a25124b58c
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Added additional PATH variables
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2019-08-29 21:37:07 -06:00 |
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Ganesh Gore
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f54a8522fa
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Log prints task stats
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2019-08-27 22:04:32 -06:00 |
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Ganesh Gore
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715adc13ff
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Failed result do not throw error
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2019-08-27 21:25:38 -06:00 |
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Ganesh Gore
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7a3ff94116
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Added blif task in travis script
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2019-08-25 01:28:21 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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c4180fad6d
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Added .gitignore to build docs locally
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2019-08-25 00:49:04 -06:00 |
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Ganesh Gore
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632c9d6976
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Added python execution path in config file
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2019-08-25 00:42:48 -06:00 |
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Ganesh Gore
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f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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Ganesh Gore
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2e3f906d40
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Solved bug in travis script file
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2019-08-23 16:03:21 -06:00 |
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tangxifan
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3fb3082447
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add more tests
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2019-08-23 14:10:01 -06:00 |
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tangxifan
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ede29aa656
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Merge branch 'refactoring' into dev
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2019-08-23 13:42:10 -06:00 |
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Ganesh Gore
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52d6a9e979
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-23 13:41:29 -06:00 |
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tangxifan
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931b042750
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refactoring module manager
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2019-08-23 12:52:01 -06:00 |
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Ganesh Gore
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82a186bf7c
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Added python3.5 in travis script
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2019-08-23 12:45:17 -06:00 |
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Ganesh Gore
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28dde899db
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Updated Architecture Template
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2019-08-23 12:44:45 -06:00 |
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tangxifan
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520630c5e2
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add more testing tasks
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2019-08-23 10:16:52 -06:00 |
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tangxifan
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732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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Ganesh Gore
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6e7de16ad4
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Solved bug in commnad rearrangement
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2019-08-22 23:41:25 -06:00 |
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Ganesh Gore
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89589ddc1c
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-22 18:46:51 -06:00 |
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Ganesh Gore
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4189ada1eb
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Fixed run test file
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2019-08-22 17:31:46 -06:00 |
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Ganesh Gore
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5027f9c4b3
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Added test mode script in travis
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2019-08-22 17:03:56 -06:00 |
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Ganesh Gore
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8f80cb3c24
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Added Sample script to run blif VPR
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2019-08-22 17:02:12 -06:00 |
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Ganesh Gore
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77e2a7bca3
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Added execution time logs in flow script
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2019-08-22 17:01:38 -06:00 |
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Ganesh Gore
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30cbe38d3d
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Added Test Modes - Added blif VPR Option
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2019-08-22 17:00:59 -06:00 |
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Ganesh Gore
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d5ce1b557e
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Made thread logs prettier
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2019-08-22 16:56:58 -06:00 |
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tangxifan
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3f45e6cc87
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remove dead codes for essential gates code generation
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2019-08-22 10:01:52 -06:00 |
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tangxifan
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43de2d7636
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some tuning on Verilog port formatting
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2019-08-21 23:47:50 -06:00 |
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tangxifan
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1be5632e92
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minor tuning on the delay assignment
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2019-08-21 23:11:54 -06:00 |