Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
tangxifan
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7f999d03c6
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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
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2021-10-30 18:05:39 -07:00 |
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tangxifan
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370e3fef83
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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
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2021-10-30 18:03:59 -07:00 |
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tangxifan
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c8e9dfbeda
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
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tangxifan
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a4cfc84930
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[Test] Bug fix
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2021-10-30 16:00:47 -07:00 |
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tangxifan
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335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
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tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
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tangxifan
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ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
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tangxifan
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40d11a45d9
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[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
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2021-10-30 14:49:56 -07:00 |
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tangxifan
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16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
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tangxifan
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9f03ecb160
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[Test] Patch test case due to the changes in counter benchmarks
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2021-07-02 17:57:39 -06:00 |
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tangxifan
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64dcdaec61
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[Test] Update all the tasks that use counter benchmark
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2021-07-02 17:29:13 -06:00 |
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tangxifan
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3cbe266c44
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[Test] Bug fix on the test case for multi-mode FF and pin constraints
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2021-07-02 15:27:27 -06:00 |
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tangxifan
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3aacce2a96
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Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 14:04:42 -06:00 |
Ganesh Gore
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edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
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tangxifan
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5286f9ba25
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[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
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2021-07-02 11:39:00 -06:00 |
ANDREW HARRIS POND
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006b54c4bc
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ready for merge
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2021-07-01 15:35:39 -06:00 |
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ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
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tangxifan
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83d177b13b
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[Test] Deploy the newly added adder benchmarks to tests
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2021-06-30 15:14:24 -06:00 |
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tangxifan
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9eeec05a1f
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[Test] Bug fix
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2021-06-29 19:55:07 -06:00 |
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tangxifan
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f32ffb6d61
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[Test] Bug fix
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2021-06-29 18:51:28 -06:00 |
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tangxifan
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c6089385b0
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[Misc] Bug fix
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2021-06-29 18:34:41 -06:00 |
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tangxifan
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5f5a03f17f
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[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
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2021-06-29 18:28:38 -06:00 |
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tangxifan
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2c1692e6dc
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[Test] Bug fix
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2021-06-29 17:54:25 -06:00 |
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tangxifan
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30c2f597f2
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[Test] Added two cases to validate testbench generation without self checking
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2021-06-29 16:06:15 -06:00 |
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tangxifan
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6f0600e17f
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[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
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2021-06-27 19:56:01 -06:00 |
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tangxifan
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477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
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f06017581c
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[Test] Bug fix in counter micro benchmark tests
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2021-06-22 16:33:50 -06:00 |
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tangxifan
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760570d883
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[Test] Update counter test case for cover most counter HDL design
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2021-06-21 18:13:18 -06:00 |
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tangxifan
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9c24a739be
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[Test] Added a MAC benchmark sweeping test
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2021-06-21 17:40:53 -06:00 |
Andrew Pond
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3cfc42cdf9
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added testbench CI
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2021-06-15 14:16:31 -06:00 |
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tangxifan
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eed30605d7
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[Test] patch test case
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2021-06-09 15:20:55 -06:00 |
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tangxifan
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52c0ed571b
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[Test] Patch test case to use proper template
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2021-06-09 14:27:02 -06:00 |
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tangxifan
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c62666e7c3
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[Test] Use proper template for some failing tests
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2021-06-09 14:24:34 -06:00 |
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tangxifan
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462326aaa5
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[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
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2021-06-07 21:50:00 -06:00 |
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tangxifan
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5ecd975ec7
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[Test] Bug fix
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2021-06-07 19:20:10 -06:00 |
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tangxifan
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9556f994b4
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[Test] Use 'write_full_testbench' in all the memory bank -related test cases
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2021-06-07 17:49:40 -06:00 |
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tangxifan
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a67196178e
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[Test] Now use 'write_full_testbench' in configuration frame test cases
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2021-06-07 13:58:15 -06:00 |
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tangxifan
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27fa15603a
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[Tool] Patch test case due to changes in the template script
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2021-06-04 18:17:47 -06:00 |
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tangxifan
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5f96d440ec
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[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
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2021-06-04 11:48:05 -06:00 |
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tangxifan
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ec203d3a5c
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[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
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2021-06-04 11:35:23 -06:00 |
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tangxifan
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2068291de0
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[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
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2021-06-04 11:32:49 -06:00 |
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tangxifan
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aa4e1f5f9a
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[Test] Update test case which uses write_full_testbench openfpga shell script
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2021-06-04 11:29:43 -06:00 |
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tangxifan
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ebe30fc070
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[Test] Deploy write full testbench to multi-head configuration chain test case
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2021-06-03 17:08:33 -06:00 |
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tangxifan
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1e9f6eb439
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[Test] update configuration chain test to use new testbench
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2021-06-03 15:53:27 -06:00 |
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tangxifan
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2baf3ddd2f
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[Test] Add test cases for 'report_bitstream_distribution' command
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2021-05-07 12:06:24 -06:00 |
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tangxifan
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f1658cb735
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[Test] Deploy blinking to test cases
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2021-05-06 15:17:45 -06:00 |