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3365 Commits

Author SHA1 Message Date
tangxifan c638e5bde5 [Doc] Update documentation for default net type option 2021-02-28 12:00:55 -07:00
tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 744d87cb4e [Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues 2021-02-26 09:34:52 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
tpagarani 013f6d8497
Merge pull request #254 from lnis-uofu/update_yosys_scr_name 
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
 2021-02-26 04:28:12 -05:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
tpagarani d38514f87e
Merge pull request #253 from lnis-uofu/update_yosys_scr_name 
Modifying custom yosys script file name
 2021-02-26 02:37:09 -05:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
tangxifan 4c2a88e27f [Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed 2021-02-24 11:51:10 -07:00
tangxifan 38f08588c8 Merge branch 'master' into dev 2021-02-24 11:23:44 -07:00
tangxifan 7a5dd1bc02 [Tools] Patch circuit library for dummy circuit models without any ports 2021-02-24 10:36:48 -07:00
tangxifan 0ce9b66c75 [Arch] Add a dummy adder lut circuit model to support HDL simulation 2021-02-24 10:09:44 -07:00
tangxifan 86a602d381 [Test] Deploy new test to CI 2021-02-23 19:55:07 -07:00
tangxifan a62786986b [Test] Turn off verification in adder lut test temporarily 2021-02-23 19:03:25 -07:00
tangxifan df7b436ac7 [Tool] Patch repacker to support duplicated nets due to adder nets 2021-02-23 19:01:18 -07:00
tangxifan ad25944e59 [Arch] Patched superLUT architecture example when trying adder8 synthesis script 2021-02-23 19:00:27 -07:00
tangxifan 53df7f69e7 [Test] Bug fix in the test case using lut adder 2021-02-23 16:59:46 -07:00
tangxifan db71cc8a16 [Test] Add LUT adder test using quicklogic synthesis script 2021-02-23 16:50:58 -07:00
tangxifan 154f3b6cfc
Merge pull request #249 from lnis-uofu/dev 
Reorganize QuickLogic's Regression Tests
 2021-02-23 08:35:27 -07:00
tangxifan 19f6b221b1 [Test] Rework comments on runtime 2021-02-22 15:25:57 -07:00
tangxifan 4803b0ce42 [Test] Add test case for sdc controller 2021-02-22 15:02:14 -07:00
tangxifan c7a9a4e896 [Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs 2021-02-22 15:01:50 -07:00
tangxifan ca135f3325 [Arch] Add flagship architecture with 8-clock 2021-02-22 15:01:18 -07:00
tangxifan 2e2b1cb6e7 [Test] Use hetergenenous FPGA architecture in quicklogic tests 2021-02-22 13:41:04 -07:00
tangxifan 1c09c55e9f [Arch] Add hetergenenous 8-clock FPGA architecture 2021-02-22 13:38:50 -07:00
tangxifan b3fed683f9 [Test] Deploy test to CI 2021-02-22 12:43:30 -07:00
tangxifan bc30f62c5a [Test] Add test for sdc controller 2021-02-22 12:41:53 -07:00
tangxifan 60dc194d8f [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
tangxifan 71e0026a50 [Test] Add new test for 5-clock counter to quicklogic tests 2021-02-22 11:32:17 -07:00
tangxifan 2bb588dacf [Flow] Add a new script for generating bitstream for multi-clock architectures 2021-02-22 11:31:24 -07:00
tangxifan 77896379e2 [Arch] Add simulation setting for 8-clock architectures 2021-02-22 11:10:03 -07:00
tangxifan 16debe49f6 [Arch] Add more comments on the 4 clock simulation setting file 2021-02-22 11:04:34 -07:00
tangxifan 0ac75723af [Arch] Add new architecture with 8 clocks 2021-02-22 11:00:45 -07:00
tangxifan b9c2564a7e [Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks 2021-02-22 10:49:21 -07:00
tangxifan bc8aa0ebc6 [Test] Remove routing test from quicklogic's flow test 2021-02-22 10:22:47 -07:00
tangxifan 2dbdc2644f [Benchmark] Remove replicate micro benchmarks 2021-02-22 10:22:19 -07:00
tangxifan 9b6b2068ee [Test] Move MCNC test to benchmark sweep test group 2021-02-22 10:18:34 -07:00
tangxifan c1f4a434e4 [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00
tangxifan 0384c4c61e Merge branch 'master' into dev 2021-02-22 09:49:03 -07:00
ganeshgore 4315660bf1
Merge pull request #245 from lnis-uofu/dev 
Throw fatal error when the number of configurable region is different between fabric key and architecture definition
 2021-02-22 09:48:23 -07:00
tangxifan d6a02a985e
Merge pull request #248 from lnis-uofu/add_quicklogic_tests 
Disabling verilog testbench generation for quicklogic tests
 2021-02-22 09:02:29 -07:00
Lalit Sharma d842026672 Disabling verilog testbench generation for quicklogic tests 2021-02-21 21:58:23 -08:00
Lalit Narain Sharma be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests 
Adding quicklogic tests and updating the corresponding conf file to r…
 2021-02-22 09:50:26 +05:30
Lalit Sharma 576e6753f6 Removing 2 more tests which are variant of and design 2021-02-19 09:11:19 -08:00
Lalit Sharma d4c5a5655a Removing blif file as well as and2 testcase 2021-02-19 08:55:17 -08:00
Lalit Sharma 6de0954ca5 Uncommenting all benchmarks except 2 that requires multiple clocks 2021-02-19 08:40:26 -08:00
tangxifan 01b9bf2a02 [Doc] Update num_region XML for config protocol 2021-02-18 21:58:30 -07:00
tangxifan e6091fb3ff [Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition 2021-02-18 21:56:30 -07:00
tangxifan bcd8256c59
Merge pull request #243 from lnis-uofu/dev 
Bug fix for truth table creation for wired LUT created by repacking
 2021-02-18 20:44:02 -07:00