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Merge pull request #253 from lnis-uofu/update_yosys_scr_name 

Modifying custom yosys script file name
This commit is contained in:
tpagarani 2021-02-26 02:37:09 -05:00 committed by GitHub
parent 154f3b6cfc 1e48d4f6dc
commit d38514f87e
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 20 additions and 26 deletions
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0
openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys → openfpga_flow/misc/qlf_k4n8_yosys.ys
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6
openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
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@ -1,6 +0,0 @@
# Yosys synthesis script for ${TOP_MODULE}
# Read verilog files
${READ_VERILOG_FILE}
synth_quicklogic -blif ${OUTPUT_BLIF} -adder -openfpga -top ${TOP_MODULE}

2
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
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@ -30,6 +30,6 @@ bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter12
[SYNTHESIS_PARAM]
bench0_top = counter120bitx5
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

36
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -48,43 +48,43 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en
[SYNTHESIS_PARAM]
bench0_top = io_tc1
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench1_top = unsigned_mult_80
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench2_top = bin2bcd
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench3_top = counter
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench5_top = rs_decoder_top
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench5_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench6_top = top_module
bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench6_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench7_top = sha256
bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench7_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench8_top = cavlc_top
bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench9_top = cf_fft_256_8
bench9_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench9_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
#bench10_top = counter120bitx5
#bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench11_top = top
bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench11_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench12_top = dct_mac
bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench12_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench13_top = des_perf
bench13_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench13_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench14_top = diffeq_f_systemC
bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench14_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench15_top = i2c_master_top
bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench16_top = iir
bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench17_top = jpeg_qnr
bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
bench18_top = multi_enc_decx2x4
# sdc_controller requires 4 clocks
#bench19_top = sdc_controller
#bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=

2
openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
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@ -38,6 +38,6 @@ bench0_top = sdc_controller
# Use standard script for now because QL synthesis recipe generates $DFF_PP model
# Also current synthesis recipe does not support FIFO, BRAM and multiplier
# which causes runtime to be long
#bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
#bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_k4n8_yosys.ys
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]