616d7706c9
Added list of intermidiate files filename
2019-08-19 19:05:08 -06:00
8f8707ff98
Added option to filter results after parsing
2019-08-19 19:04:14 -06:00
5116aa2ae1
Added architecture and replaced variables
2019-08-19 19:02:50 -06:00
cb5b16c949
Moved required files to openfpga folder
2019-08-19 18:57:42 -06:00
6dc05b769b
Added Power Model Files
2019-08-19 18:55:23 -06:00
7f6c1b3e00
Code re-arrangement
...
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
fb29fcfc06
Added build files in .gitignore
2019-08-17 22:59:54 -06:00
12c998c12a
Added dockerignore + minor changes in openfpga_flow script
2019-08-17 16:22:52 -06:00
66bb8a5e4b
Updated RRAM architecture file
2019-08-17 02:20:04 -06:00
7bfc48b8e4
Moved spice and verilog netlist folder location
2019-08-17 01:49:49 -06:00
125d7888df
Merge remote-tracking branch 'origin/spice_model_refactoring' into ganesh_dev
2019-08-16 22:00:41 -06:00
aa7f3bef7f
fixed bugs in configure pb_rr_graph and dependence on testbenches
2019-08-16 18:20:30 -06:00
e456b6f905
replace spice_models with circuit model in bitstream generator
2019-08-16 16:36:49 -06:00
5ece7ab6d0
start refactoring the bitstream part using spice_models
2019-08-16 15:58:14 -06:00
b66e120366
patch on local encoders for unused configuration, avoid chip-burn issues
2019-08-16 15:32:23 -06:00
4865335627
Merge remote-tracking branch 'origin/dev' into ganesh_dev
2019-08-16 14:14:16 -06:00
c43c3cdf25
Added VPR output parse option
2019-08-16 13:36:39 -06:00
effbd332aa
Added task report generation
2019-08-16 10:59:44 -06:00
901932a4fc
First draft: Working openfpga task flow
2019-08-16 09:44:50 -06:00
4eb046760b
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
2019-08-15 21:57:59 -06:00
5d3708651e
Added fpga_flow and fpga_task script
...
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
35ad4a87e5
add travis slack notification
2019-08-14 12:51:17 -06:00
8e38aa6019
Merge with heterogeneous for unfracturable LUT bug fix
2019-08-14 10:10:27 -06:00
df873903f8
Bug fix for non fracturable LUT
2019-08-14 09:32:15 -06:00
30c0f2b6b7
Merge remote-tracking branch 'origin/dev' into heterogeneous
2019-08-14 09:11:54 -06:00
90aaed6e1f
Fix regression test
2019-08-14 09:10:13 -06:00
d2d8af5416
bug fixing for pb_type num_conf_bits and num_iopads stats
2019-08-13 17:34:09 -06:00
edfa72a666
try to fix the bug in clock net identification
2019-08-13 16:47:28 -06:00
1118b28397
use single subckt for switch box again, to abolish the multi-module subckt
2019-08-13 16:11:04 -06:00
4cffd8ac2d
keep route file updated with tileable rr_graph
2019-08-13 15:37:42 -06:00
c7526cb43c
memory sanitized
2019-08-13 14:19:40 -06:00
ef4d15df4e
reorganize the libarchfpga repository
2019-08-13 13:37:35 -06:00
392f579836
add linking functions for circuit models and architecture, memory sanitizing is ongoing
2019-08-13 13:25:23 -06:00
8dab4dec90
Merge remote-tracking branch 'origin/dev' into heterogeneous
2019-08-13 11:09:29 -06:00
7851246424
Resolve merge issue
2019-08-13 11:08:30 -06:00
c56f289d3e
add checkers for circuit library
2019-08-12 16:45:33 -06:00
d4ae160d3a
start adding circuit library checkers
2019-08-12 14:20:11 -06:00
2da4d3f33c
Merge remote-tracking branch 'origin/dev' into heterogeneous
2019-08-12 09:57:02 -06:00
fbdab32a2d
timing graph for circuit models are working
2019-08-10 13:03:24 -06:00
c004699a14
complete parsers for ports
2019-08-09 21:00:41 -06:00
2c7d6e3de4
adding port parsers
2019-08-09 17:48:55 -06:00
9ab57d1b2e
Added fpga_flow script - Working Yosys
2019-08-09 16:49:05 -06:00
f80e58c753
developing a in-house tokenizer
2019-08-09 16:36:22 -06:00
3d7adb3dd9
start developing parsers for delay values
2019-08-09 15:52:28 -06:00
6b5ac2e1ef
add timing graph builder for circuit models
2019-08-09 12:45:03 -06:00
b82369dd96
Added first draft of fpga_task script
2019-08-09 00:17:06 -06:00
c8d04c4f00
plug in fast look-up builder
2019-08-08 21:20:28 -06:00
0cc439f76c
Working lattice benchmark unclean commit
2019-08-08 18:08:39 -06:00
158c67075e
built a conversion from spice_models to circuit_library and plug in
2019-08-08 17:25:27 -06:00
0b46adb5ef
Correction to the explicit Verilog for FPGAs above 2x2
2019-08-08 15:17:43 -06:00
Ganesh Gore
tangxifan
AurelienUoU
Baudouin Chauviere