tangxifan
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c7ade72200
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[core] code complete for the core wrapper creator. Start debugging
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2023-06-18 19:17:42 -07:00 |
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tangxifan
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8bc70b590a
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[core] developing fpga_core insertion
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2023-06-17 23:42:45 -07:00 |
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tangxifan
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46510388be
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[core] now fabric generator can wire clock ports to routing blocks
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2023-03-02 12:33:26 -08:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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b87b7a99c5
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[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
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tangxifan
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2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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tangxifan
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cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
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e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
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552dddffd0
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[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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adee87569d
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enable fast bitstream building by creating a frame view of fabric
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2020-07-02 16:25:36 -06:00 |
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tangxifan
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a5055e9d26
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add support about loading external fabric key
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2020-06-12 13:03:11 -06:00 |
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tangxifan
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9dbf536306
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add shuffled configurable children support for top module
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2020-06-12 11:16:53 -06:00 |
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tangxifan
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ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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290dd1a8a6
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add frame decoder builder to all the module graph builder except the top-level
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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8864920460
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add frame-based memory module builder
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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b3796b0818
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build io location map
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2020-02-26 19:58:18 -07:00 |
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tangxifan
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85627dc128
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put build top module online
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2020-02-15 14:13:32 -07:00 |
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tangxifan
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afe8278670
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put routing module builder online
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2020-02-13 17:35:29 -07:00 |
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tangxifan
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89086ed080
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add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
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072965cd64
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make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
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002c2795fe
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add memory module builder
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2020-02-12 20:06:38 -07:00 |
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tangxifan
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8e381f0581
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add wire module builder
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2020-02-12 19:57:15 -07:00 |
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tangxifan
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e842150cc5
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add lut module builder
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2020-02-12 19:52:41 -07:00 |
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tangxifan
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fddd3c9463
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add mux module builder
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2020-02-12 19:45:14 -07:00 |
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tangxifan
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ea7d879b4f
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add decoder module builder
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2020-02-12 18:28:50 -07:00 |
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tangxifan
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f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |