tangxifan
|
bd6a0c6a55
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refactored grid instance addition to top module
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2019-10-14 17:47:10 -06:00 |
|
tangxifan
|
f779ad7ecf
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bug fixing for global and gpio port wiring; start refactoring top-level module
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2019-10-14 15:53:04 -06:00 |
|
tangxifan
|
6793c67c8d
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refactored pb_type and grid Verilog generation
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2019-10-13 21:07:30 -06:00 |
|
tangxifan
|
b581399761
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add memory ports and nets to intermediate pb_types
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2019-10-13 17:45:32 -06:00 |
|
tangxifan
|
cab4bd6807
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add gpio ports to pb_type modules
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2019-10-13 16:23:22 -06:00 |
|
tangxifan
|
0f50251b3b
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add mux and associated memory modules in refactoring Verilog generation for pb_types
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2019-10-13 11:11:19 -06:00 |
|
tangxifan
|
85644d07ae
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refactoring pb interc Verilog generation
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2019-10-12 21:55:53 -06:00 |
|
tangxifan
|
d1948c82eb
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Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
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2019-10-11 21:43:47 -06:00 |
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tangxifan
|
b3ca0d32a4
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remove configuration bus naming dependency on SRAM circuit models
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2019-10-11 19:47:36 -06:00 |
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tangxifan
|
73a5977e0d
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Debugged Verilog generation for primitive pb_types
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2019-10-11 18:00:37 -06:00 |
|
tangxifan
|
50f7d1eae3
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bug fixing in Verilog port merging and instanciation
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2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
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refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
|
c9950162d1
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start plug in new Verilog writer. Start debugging
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2019-10-10 22:02:46 -06:00 |
|
tangxifan
|
1f650aac73
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add local direct connection Verilog code generation
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2019-10-10 20:54:31 -06:00 |
|
tangxifan
|
f2b3341d87
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developing verilog writer for generic module graph
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2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
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developing verilog writer for modules
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2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
9cb6e64ab3
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refactoring instanciation inside primitive pb_type Verilog module
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2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
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add wire connection in Verilog module declaration
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2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
6bed89c237
|
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
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2019-10-08 18:00:04 -06:00 |
|
tangxifan
|
ea2942640e
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
|
tangxifan
|
512e9f4e8e
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refactoring Verilog generation for primitive pb_types
|
2019-10-08 12:10:26 -06:00 |
|
tangxifan
|
173b886314
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add module name generation for pb_types
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2019-10-07 21:09:54 -06:00 |
|
tangxifan
|
86c9af872e
|
refactoring physical block Verilog generation
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2019-10-07 17:39:00 -06:00 |
|
tangxifan
|
997bfdbb95
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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tangxifan
|
3ca6f08aa4
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start refactoring physical block Verilog generation
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2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
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refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |
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tangxifan
|
393f0b0ac3
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align formal verification port inside refactored routing blocks
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2019-10-05 21:16:48 -06:00 |
|
tangxifan
|
86387ff79c
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Merge branch 'refactoring' into dev
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2019-10-05 18:15:31 -06:00 |
|
tangxifan
|
c920047ee8
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refactored Verilog generation for connection blocks
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2019-10-05 18:14:23 -06:00 |
|
tangxifan
|
2d7e8d9811
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add check codes for memory buses
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2019-10-05 11:07:26 -06:00 |
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tangxifan
|
6b301d9f44
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Merge branch 'dev' into refactoring
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2019-10-04 22:47:29 -06:00 |
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tangxifan
|
b905c0c68c
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refactored memory module Verilog generation for scan-chains
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2019-10-04 22:45:45 -06:00 |
AurelienUoU
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7aa24f407e
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Fix explicit port name in CBs
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2019-10-04 11:20:46 -06:00 |
Baudouin Chauviere
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6f7023658e
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Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though"
This reverts commit 95596bb4f8.
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2019-10-03 14:59:04 -06:00 |
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Baudouin Chauviere
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95596bb4f8
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Correction on the cb vs sb corrdinator. Does not fix the problem though
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2019-10-03 13:50:01 -06:00 |
|
Baudouin Chauviere
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01ff484158
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Explicit verilog passing all tests
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2019-10-02 10:22:28 -06:00 |
|
Baudouin Chauviere
|
6b3e1fd410
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Get backup verilog_routing.c
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2019-10-02 08:54:56 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
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Hot fix
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2019-10-01 16:40:16 -06:00 |
|
Baudouin Chauviere
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633a12ee08
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Buggy version but need help on debugging
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2019-10-01 14:49:42 -06:00 |
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tangxifan
|
b082e60c10
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start refactoring instanciation of memory modules
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2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
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simplify the local wire generation for ccffs
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2019-09-28 21:36:56 -06:00 |
|
tangxifan
|
1983e56557
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make local configuration bus generation more general
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2019-09-28 21:02:14 -06:00 |
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tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
|
4da5035627
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Connect CCFFs in a chain in a Verilog module
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2019-09-27 20:50:12 -06:00 |
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tangxifan
|
f0949fea2f
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Merge branch 'dev' into refactoring
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2019-09-27 18:09:58 -06:00 |
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tangxifan
|
1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
|
AurelienUoU
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640922accd
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-27 16:54:13 -06:00 |
|
AurelienUoU
|
a93d7e57f7
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Scan chain support in directlist
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2019-09-27 16:53:00 -06:00 |
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tangxifan
|
167778cf57
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refactoring MUX Verilog instanciation in Switch block
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2019-09-27 16:05:47 -06:00 |