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1033 Commits

Author SHA1 Message Date
tangxifan bd6a0c6a55 refactored grid instance addition to top module 2019-10-14 17:47:10 -06:00
tangxifan f779ad7ecf bug fixing for global and gpio port wiring; start refactoring top-level module 2019-10-14 15:53:04 -06:00
tangxifan 6793c67c8d refactored pb_type and grid Verilog generation 2019-10-13 21:07:30 -06:00
tangxifan b581399761 add memory ports and nets to intermediate pb_types 2019-10-13 17:45:32 -06:00
tangxifan cab4bd6807 add gpio ports to pb_type modules 2019-10-13 16:23:22 -06:00
tangxifan 0f50251b3b add mux and associated memory modules in refactoring Verilog generation for pb_types 2019-10-13 11:11:19 -06:00
tangxifan 85644d07ae refactoring pb interc Verilog generation 2019-10-12 21:55:53 -06:00
tangxifan a65b76c25a Merge branch 'dev' into refactoring 2019-10-12 18:24:03 -06:00
tangxifan 08df0fd585
Merge pull request #30 from LNIS-Projects/master 
Update README from Tim
 2019-10-12 11:19:05 -06:00
tangxifan d1948c82eb Refactoring Verilog generation intermediate level of pb_types and SRAM port generation 2019-10-11 21:43:47 -06:00
tangxifan 49a8273482
Merge pull request #29 from mithro/patch-1 
Small formatting fixes to the README
 2019-10-11 20:16:56 -06:00
tangxifan b3ca0d32a4 remove configuration bus naming dependency on SRAM circuit models 2019-10-11 19:47:36 -06:00
tangxifan 73a5977e0d Debugged Verilog generation for primitive pb_types 2019-10-11 18:00:37 -06:00
tangxifan 50f7d1eae3 bug fixing in Verilog port merging and instanciation 2019-10-11 14:20:04 -06:00
tangxifan 663b1b7665 refactorint net addition for configuration signals in module graph 2019-10-11 13:07:14 -06:00
tangxifan c9950162d1 start plug in new Verilog writer. Start debugging 2019-10-10 22:02:46 -06:00
tangxifan 1f650aac73 add local direct connection Verilog code generation 2019-10-10 20:54:31 -06:00
Tim Ansell 916cfa27ed
Small formatting fixes to the README 
* Make the compile steps easy to copy.
 * Small wording fixes.
 * Use relative links (github rewrites them).
 * Remove unneeded `<br>` tags.
 2019-10-10 19:39:44 -07:00
tangxifan f2b3341d87 developing verilog writer for generic module graph 2019-10-10 20:09:55 -06:00
tangxifan e5956467fd developing verilog writer for modules 2019-10-10 14:43:32 -06:00
tangxifan edad988ebb add net accessor and mutators to module manager 2019-10-09 21:14:30 -06:00
tangxifan 557d8b60f3 start implementing module graph-based connection 2019-10-09 20:30:16 -06:00
tangxifan 9cb6e64ab3 refactoring instanciation inside primitive pb_type Verilog module 2019-10-08 21:29:42 -06:00
tangxifan 6f42aac626 add wire connection in Verilog module declaration 2019-10-08 20:14:38 -06:00
tangxifan 6bed89c237 refactored counting config bits for circuit model and update Verilog generation for primitive pb_types 2019-10-08 18:00:04 -06:00
tangxifan ea2942640e refactored port addition for pb_types in Verilog generation 2019-10-08 14:03:17 -06:00
tangxifan 512e9f4e8e refactoring Verilog generation for primitive pb_types 2019-10-08 12:10:26 -06:00
tangxifan 173b886314 add module name generation for pb_types 2019-10-07 21:09:54 -06:00
tangxifan 86c9af872e refactoring physical block Verilog generation 2019-10-07 17:39:00 -06:00
tangxifan 997bfdbb95 move the refactored function for physical block Verilog generation to a new source file 2019-10-07 16:03:15 -06:00
tangxifan 3ca6f08aa4 start refactoring physical block Verilog generation 2019-10-06 19:27:55 -06:00
tangxifan 1e183e7885 refactored shared config bits calculation 2019-10-06 16:57:53 -06:00
tangxifan 393f0b0ac3 align formal verification port inside refactored routing blocks 2019-10-05 21:16:48 -06:00
tangxifan 86387ff79c Merge branch 'refactoring' into dev 2019-10-05 18:15:31 -06:00
tangxifan c920047ee8 refactored Verilog generation for connection blocks 2019-10-05 18:14:23 -06:00
AurelienUoU 0983f85684 Merge remote-tracking branch 'origin/dev' into heterogeneous 2019-10-05 12:46:34 -06:00
Baudouin Chauviere 027272c976 Faster regression test 2019-10-05 12:10:55 -06:00
tangxifan 2d7e8d9811 add check codes for memory buses 2019-10-05 11:07:26 -06:00
tangxifan 6b301d9f44 Merge branch 'dev' into refactoring 2019-10-04 22:47:29 -06:00
tangxifan b905c0c68c refactored memory module Verilog generation for scan-chains 2019-10-04 22:45:45 -06:00
AurelienUoU 7aa24f407e Fix explicit port name in CBs 2019-10-04 11:20:46 -06:00
Baudouin Chauviere 6f7023658e Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though" 
This reverts commit 95596bb4f8.
 2019-10-03 14:59:04 -06:00
Baudouin Chauviere 95596bb4f8 Correction on the cb vs sb corrdinator. Does not fix the problem though 2019-10-03 13:50:01 -06:00
Baudouin Chauviere db059af8b8 Lighten the regression test 2019-10-03 13:33:28 -06:00
Baudouin Chauviere c7e1f7d90b Added explicit_verilog to regression test in a clean way 2019-10-03 10:17:04 -06:00
Baudouin Chauviere 01ff484158 Explicit verilog passing all tests 2019-10-02 10:22:28 -06:00
Baudouin Chauviere 6b3e1fd410 Get backup verilog_routing.c 2019-10-02 08:54:56 -06:00
Baudouin Chauviere 829cbcfbe3 Merge 
Merge remote-tracking branch 'origin' into explicit_verilog
 2019-10-01 16:54:27 -06:00
Baudouin Chauviere 33e50bbc8c fix 2019-10-01 16:54:16 -06:00
Baudouin Chauviere 7c3ab38410 Hot fix 2019-10-01 16:40:16 -06:00